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authorSoren Brinkmann <soren.brinkmann@xilinx.com>2012-12-19 18:18:37 (GMT)
committerMichal Simek <michal.simek@xilinx.com>2013-01-28 12:27:21 (GMT)
commitaf7f032dba8ccf7ee430a48656d25565672a6074 (patch)
tree00594280fae0fed8a1fdc951cd46104f63922188 /arch/arm/mach-zynq
parentf184c5caa983940305b37f428a6bfc22105235e4 (diff)
downloadlinux-af7f032dba8ccf7ee430a48656d25565672a6074.tar.xz
arm: zynq: timer: Remove unnecessary register write
Acknowedging an interrupt requires to read the interrupt register only. The write was only required to work around a bug in the QEMU implementation of the TTC, which is fixed. Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Acked-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Tested-by: Josh Cartwright <josh.cartwright@ni.com>
Diffstat (limited to 'arch/arm/mach-zynq')
-rw-r--r--arch/arm/mach-zynq/timer.c3
1 files changed, 1 insertions, 2 deletions
diff --git a/arch/arm/mach-zynq/timer.c b/arch/arm/mach-zynq/timer.c
index 570491d..f1d224b 100644
--- a/arch/arm/mach-zynq/timer.c
+++ b/arch/arm/mach-zynq/timer.c
@@ -121,8 +121,7 @@ static irqreturn_t xttcps_clock_event_interrupt(int irq, void *dev_id)
struct xttcps_timer *timer = &xttce->xttc;
/* Acknowledge the interrupt and call event handler */
- __raw_writel(__raw_readl(timer->base_addr + XTTCPS_ISR_OFFSET),
- timer->base_addr + XTTCPS_ISR_OFFSET);
+ __raw_readl(timer->base_addr + XTTCPS_ISR_OFFSET);
xttce->ce.event_handler(&xttce->ce);