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| author | Lucas De Marchi <lucas.demarchi@profusion.mobi> | 2011-03-31 01:57:33 (GMT) |
|---|---|---|
| committer | Lucas De Marchi <lucas.demarchi@profusion.mobi> | 2011-03-31 14:26:23 (GMT) |
| commit | 25985edcedea6396277003854657b5f3cb31a628 (patch) | |
| tree | f026e810210a2ee7290caeb737c23cb6472b7c38 /arch/arm/mm/cache-v7.S | |
| parent | 6aba74f2791287ec407e0f92487a725a25908067 (diff) | |
| download | linux-25985edcedea6396277003854657b5f3cb31a628.tar.xz | |
Fix common misspellings
Fixes generated by 'codespell' and manually reviewed.
Signed-off-by: Lucas De Marchi <lucas.demarchi@profusion.mobi>
Diffstat (limited to 'arch/arm/mm/cache-v7.S')
| -rw-r--r-- | arch/arm/mm/cache-v7.S | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/mm/cache-v7.S b/arch/arm/mm/cache-v7.S index 6136e68..dc18d81 100644 --- a/arch/arm/mm/cache-v7.S +++ b/arch/arm/mm/cache-v7.S @@ -96,7 +96,7 @@ ENDPROC(v7_flush_dcache_all) * Flush the entire cache system. * The data cache flush is now achieved using atomic clean / invalidates * working outwards from L1 cache. This is done using Set/Way based cache - * maintainance instructions. + * maintenance instructions. * The instruction cache can still be invalidated back to the point of * unification in a single instruction. * |