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authorRussell King <rmk@dyn-67.arm.linux.org.uk>2006-06-29 17:24:21 (GMT)
committerRussell King <rmk+kernel@arm.linux.org.uk>2006-06-29 17:24:21 (GMT)
commit8799ee9f49f6171fd58f4d64f8c067ca49006a5d (patch)
treeb746b8800bc99633f31505d151624c8ccd75cd47 /arch/arm/mm/proc-arm720.S
parent326764a85b7676388db3ebad6488f312631d7661 (diff)
downloadlinux-8799ee9f49f6171fd58f4d64f8c067ca49006a5d.tar.xz
[ARM] Set bit 4 on section mappings correctly depending on CPU
On some CPUs, bit 4 of section mappings means "update the cache when written to". On others, this bit is required to be one, and others it's required to be zero. Finally, on ARMv6 and above, setting it turns on "no execute" and prevents speculative prefetches. With all these combinations, no one value fits all CPUs, so we have to pick a value depending on the CPU type, and the area we're mapping. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mm/proc-arm720.S')
-rw-r--r--arch/arm/mm/proc-arm720.S8
1 files changed, 8 insertions, 0 deletions
diff --git a/arch/arm/mm/proc-arm720.S b/arch/arm/mm/proc-arm720.S
index 8610246..fb4110a 100644
--- a/arch/arm/mm/proc-arm720.S
+++ b/arch/arm/mm/proc-arm720.S
@@ -246,6 +246,10 @@ __arm710_proc_info:
PMD_BIT4 | \
PMD_SECT_AP_WRITE | \
PMD_SECT_AP_READ
+ .long PMD_TYPE_SECT | \
+ PMD_BIT4 | \
+ PMD_SECT_AP_WRITE | \
+ PMD_SECT_AP_READ
b __arm710_setup @ cpu_flush
.long cpu_arch_name @ arch_name
.long cpu_elf_name @ elf_name
@@ -267,6 +271,10 @@ __arm720_proc_info:
PMD_BIT4 | \
PMD_SECT_AP_WRITE | \
PMD_SECT_AP_READ
+ .long PMD_TYPE_SECT | \
+ PMD_BIT4 | \
+ PMD_SECT_AP_WRITE | \
+ PMD_SECT_AP_READ
b __arm720_setup @ cpu_flush
.long cpu_arch_name @ arch_name
.long cpu_elf_name @ elf_name