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| author | Santosh Shilimkar <santosh.shilimkar@ti.com> | 2011-06-28 19:42:56 (GMT) |
|---|---|---|
| committer | Santosh Shilimkar <santosh.shilimkar@ti.com> | 2011-09-23 06:35:30 (GMT) |
| commit | 8fb54284ba6aa1f0d832ec015fde64ecf4bb0f4f (patch) | |
| tree | 1c9a5d9f0c57af407085f2d74ef8c3bd63ecb34e /arch/arm/mm | |
| parent | 48af9feab5e3bdf21af3a929ecc7c0b79d9a4a4e (diff) | |
| download | linux-8fb54284ba6aa1f0d832ec015fde64ecf4bb0f4f.tar.xz | |
ARM: mm: Add strongly ordered descriptor support.
On certain architectures, there might be a need to mark certain
addresses with strongly ordered memory attributes to avoid ordering
issues at the interconnect level.
On OMAP4, the asynchronous bridge buffers can only be drained
with strongly ordered accesses and hence the need to mark the
memory strongly ordered.
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Woodruff Richard <r-woodruff2@ti.com>
Tested-by: Vishwanath BS <vishwanath.bs@ti.com>
Diffstat (limited to 'arch/arm/mm')
| -rw-r--r-- | arch/arm/mm/mmu.c | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c index 594d677..ea9c9f3 100644 --- a/arch/arm/mm/mmu.c +++ b/arch/arm/mm/mmu.c @@ -273,6 +273,14 @@ static struct mem_type mem_types[] = { .prot_l1 = PMD_TYPE_TABLE, .domain = DOMAIN_KERNEL, }, + [MT_MEMORY_SO] = { + .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY | + L_PTE_MT_UNCACHED, + .prot_l1 = PMD_TYPE_TABLE, + .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_S | + PMD_SECT_UNCACHED | PMD_SECT_XN, + .domain = DOMAIN_KERNEL, + }, }; const struct mem_type *get_mem_type(unsigned int type) |