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authorLinus Torvalds <torvalds@linux-foundation.org>2008-07-14 23:06:58 (GMT)
committerLinus Torvalds <torvalds@linux-foundation.org>2008-07-14 23:06:58 (GMT)
commit85082fd7cbe3173198aac0eb5e85ab1edcc6352c (patch)
treeedbc09b7945994f78668d218fa02e991c3b3b365 /arch/arm/plat-mxc/irq.c
parent666484f0250db2e016948d63b3ef33e202e3b8d0 (diff)
parent53ffe3b440aa85af6fc4eda09b2d44bcdd312d4d (diff)
downloadlinux-85082fd7cbe3173198aac0eb5e85ab1edcc6352c.tar.xz
Merge branch 'for-linus' of master.kernel.org:/home/rmk/linux-2.6-arm
* 'for-linus' of master.kernel.org:/home/rmk/linux-2.6-arm: (241 commits) [ARM] 5171/1: ep93xx: fix compilation of modules using clocks [ARM] 5133/2: at91sam9g20 defconfig file [ARM] 5130/4: Support for the at91sam9g20 [ARM] 5160/1: IOP3XX: gpio/gpiolib support [ARM] at91: Fix NAND FLASH timings for at91sam9x evaluation kits. [ARM] 5084/1: zylonite: Register AC97 device [ARM] 5085/2: PXA: Move AC97 over to the new central device declaration model [ARM] 5120/1: pxa: correct platform driver names for PXA25x and PXA27x UDC drivers [ARM] 5147/1: pxaficp_ir: drop pxa_gpio_mode calls, as pin setting [ARM] 5145/1: PXA2xx: provide api to control IrDA pins state [ARM] 5144/1: pxaficp_ir: cleanup includes [ARM] pxa: remove pxa_set_cken() [ARM] pxa: allow clk aliases [ARM] Feroceon: don't disable BPU on boot [ARM] Orion: LED support for HP mv2120 [ARM] Orion: add RD88F5181L-FXO support [ARM] Orion: add RD88F5181L-GE support [ARM] Orion: add Netgear WNR854T support [ARM] s3c2410_defconfig: update for current build [ARM] Acer n30: Minor style and indentation fixes. ...
Diffstat (limited to 'arch/arm/plat-mxc/irq.c')
-rw-r--r--arch/arm/plat-mxc/irq.c70
1 files changed, 54 insertions, 16 deletions
diff --git a/arch/arm/plat-mxc/irq.c b/arch/arm/plat-mxc/irq.c
index 2ad5a69..1fbe01d 100644
--- a/arch/arm/plat-mxc/irq.c
+++ b/arch/arm/plat-mxc/irq.c
@@ -1,24 +1,59 @@
/*
- * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
*/
-/*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include <linux/module.h>
-#include <linux/moduleparam.h>
-#include <linux/init.h>
-#include <linux/device.h>
-#include <linux/errno.h>
-#include <asm/hardware.h>
+#include <linux/irq.h>
#include <asm/io.h>
-#include <asm/irq.h>
-#include <asm/mach/irq.h>
#include <asm/arch/common.h>
+#define AVIC_BASE IO_ADDRESS(AVIC_BASE_ADDR)
+#define AVIC_INTCNTL (AVIC_BASE + 0x00) /* int control reg */
+#define AVIC_NIMASK (AVIC_BASE + 0x04) /* int mask reg */
+#define AVIC_INTENNUM (AVIC_BASE + 0x08) /* int enable number reg */
+#define AVIC_INTDISNUM (AVIC_BASE + 0x0C) /* int disable number reg */
+#define AVIC_INTENABLEH (AVIC_BASE + 0x10) /* int enable reg high */
+#define AVIC_INTENABLEL (AVIC_BASE + 0x14) /* int enable reg low */
+#define AVIC_INTTYPEH (AVIC_BASE + 0x18) /* int type reg high */
+#define AVIC_INTTYPEL (AVIC_BASE + 0x1C) /* int type reg low */
+#define AVIC_NIPRIORITY7 (AVIC_BASE + 0x20) /* norm int priority lvl7 */
+#define AVIC_NIPRIORITY6 (AVIC_BASE + 0x24) /* norm int priority lvl6 */
+#define AVIC_NIPRIORITY5 (AVIC_BASE + 0x28) /* norm int priority lvl5 */
+#define AVIC_NIPRIORITY4 (AVIC_BASE + 0x2C) /* norm int priority lvl4 */
+#define AVIC_NIPRIORITY3 (AVIC_BASE + 0x30) /* norm int priority lvl3 */
+#define AVIC_NIPRIORITY2 (AVIC_BASE + 0x34) /* norm int priority lvl2 */
+#define AVIC_NIPRIORITY1 (AVIC_BASE + 0x38) /* norm int priority lvl1 */
+#define AVIC_NIPRIORITY0 (AVIC_BASE + 0x3C) /* norm int priority lvl0 */
+#define AVIC_NIVECSR (AVIC_BASE + 0x40) /* norm int vector/status */
+#define AVIC_FIVECSR (AVIC_BASE + 0x44) /* fast int vector/status */
+#define AVIC_INTSRCH (AVIC_BASE + 0x48) /* int source reg high */
+#define AVIC_INTSRCL (AVIC_BASE + 0x4C) /* int source reg low */
+#define AVIC_INTFRCH (AVIC_BASE + 0x50) /* int force reg high */
+#define AVIC_INTFRCL (AVIC_BASE + 0x54) /* int force reg low */
+#define AVIC_NIPNDH (AVIC_BASE + 0x58) /* norm int pending high */
+#define AVIC_NIPNDL (AVIC_BASE + 0x5C) /* norm int pending low */
+#define AVIC_FIPNDH (AVIC_BASE + 0x60) /* fast int pending high */
+#define AVIC_FIPNDL (AVIC_BASE + 0x64) /* fast int pending low */
+
+#define SYSTEM_PREV_REG IO_ADDRESS(IIM_BASE_ADDR + 0x20)
+#define SYSTEM_SREV_REG IO_ADDRESS(IIM_BASE_ADDR + 0x24)
+#define IIM_PROD_REV_SH 3
+#define IIM_PROD_REV_LEN 5
+
/* Disable interrupt number "irq" in the AVIC */
static void mxc_mask_irq(unsigned int irq)
{
@@ -32,7 +67,7 @@ static void mxc_unmask_irq(unsigned int irq)
}
static struct irq_chip mxc_avic_chip = {
- .mask_ack = mxc_mask_irq,
+ .ack = mxc_mask_irq,
.mask = mxc_mask_irq,
.unmask = mxc_unmask_irq,
};
@@ -71,5 +106,8 @@ void __init mxc_init_irq(void)
reg |= (0xF << 28);
__raw_writel(reg, AVIC_NIPRIORITY6);
+ /* init architectures chained interrupt handler */
+ mxc_register_gpios();
+
printk(KERN_INFO "MXC IRQ initialized\n");
}