diff options
| author | Ben Dooks <ben-linux@fluff.org> | 2008-12-12 00:24:08 (GMT) |
|---|---|---|
| committer | Ben Dooks <ben-linux@fluff.org> | 2009-03-08 12:33:51 (GMT) |
| commit | 2261e0e6e3991d4c5f33e9fedadfc465eedc05a7 (patch) | |
| tree | aa0125f362a24ecaf0cc69ff3715fecf098b4791 /arch/arm/plat-s3c24xx/include | |
| parent | 549c7e33aeb9bfe441ecf68639d2227bb90978e7 (diff) | |
| download | linux-2261e0e6e3991d4c5f33e9fedadfc465eedc05a7.tar.xz | |
[ARM] S3C: Move plat-s3c24xx pm.c support into plat-s3c
Move parts of the core and debug suspend code into the
plat-s3c for use with the new s3c64xx code.
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
Diffstat (limited to 'arch/arm/plat-s3c24xx/include')
| -rw-r--r-- | arch/arm/plat-s3c24xx/include/plat/pm-core.h | 59 |
1 files changed, 59 insertions, 0 deletions
diff --git a/arch/arm/plat-s3c24xx/include/plat/pm-core.h b/arch/arm/plat-s3c24xx/include/plat/pm-core.h new file mode 100644 index 0000000..c758821 --- /dev/null +++ b/arch/arm/plat-s3c24xx/include/plat/pm-core.h @@ -0,0 +1,59 @@ +/* linux/arch/arm/plat-s3c24xx/include/plat/pll.h + * + * Copyright 2008 Simtec Electronics + * Ben Dooks <ben@simtec.co.uk> + * http://armlinux.simtec.co.uk/ + * + * S3C24xx - PM core support for arch/arm/plat-s3c/pm.c + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +static inline void s3c_pm_debug_init_uart(void) +{ + unsigned long tmp = __raw_readl(S3C2410_CLKCON); + + /* re-start uart clocks */ + tmp |= S3C2410_CLKCON_UART0; + tmp |= S3C2410_CLKCON_UART1; + tmp |= S3C2410_CLKCON_UART2; + + __raw_writel(tmp, S3C2410_CLKCON); + udelay(10); +} + +static inline void s3c_pm_arch_prepare_irqs(void) +{ + __raw_writel(s3c_irqwake_intmask, S3C2410_INTMSK); + __raw_writel(s3c_irqwake_eintmask, S3C2410_EINTMASK); + + /* ack any outstanding external interrupts before we go to sleep */ + + __raw_writel(__raw_readl(S3C2410_EINTPEND), S3C2410_EINTPEND); + __raw_writel(__raw_readl(S3C2410_INTPND), S3C2410_INTPND); + __raw_writel(__raw_readl(S3C2410_SRCPND), S3C2410_SRCPND); + +} + +static inline void s3c_pm_arch_stop_clocks(void) +{ + __raw_writel(0x00, S3C2410_CLKCON); /* turn off clocks over sleep */ +} + +static void s3c_pm_show_resume_irqs(int start, unsigned long which, + unsigned long mask); + +static inline void s3c_pm_arch_show_resume_irqs(void) +{ + S3C_PMDBG("post sleep: IRQs 0x%08x, 0x%08x\n", + __raw_readl(S3C2410_SRCPND), + __raw_readl(S3C2410_EINTPEND)); + + s3c_pm_show_resume_irqs(IRQ_EINT0, __raw_readl(S3C2410_SRCPND), + s3c_irqwake_intmask); + + s3c_pm_show_resume_irqs(IRQ_EINT4-4, __raw_readl(S3C2410_EINTPEND), + s3c_irqwake_eintmask); +} |