diff options
| author | Yuantian Tang <andy.tang@nxp.com> | 2017-05-18 07:33:15 (GMT) |
|---|---|---|
| committer | Xie Xiaobo <xiaobo.xie@nxp.com> | 2017-07-14 09:57:25 (GMT) |
| commit | 281e406f2466e7414a1a74d5352c8b2a948669ef (patch) | |
| tree | 15f6e7308cff1a4d0ec1a8328b0eea6362bc7b52 /arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi | |
| parent | 7d423506c6221be64d68cb9795d6eb2c76472251 (diff) | |
| download | linux-281e406f2466e7414a1a74d5352c8b2a948669ef.tar.xz | |
arm64: dts: Add coreclk for ls1012a
ls1012a has separate input root clocks for core PLLs versus the
platform PLL, with the latter described as sysclk in the hw docs.
Signed-off-by: Tang Yuantian <andy.tang@nxp.com>
Diffstat (limited to 'arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi | 12 |
1 files changed, 10 insertions, 2 deletions
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi index 52e95ae..2d97fa1 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi @@ -76,10 +76,17 @@ sysclk: sysclk { compatible = "fixed-clock"; #clock-cells = <0>; - clock-frequency = <100000000>; + clock-frequency = <125000000>; clock-output-names = "sysclk"; }; + coreclk: coreclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + clock-output-names = "coreclk"; + }; + timer { compatible = "arm,armv8-timer"; interrupts = <1 13 IRQ_TYPE_LEVEL_LOW>,/* Physical Secure PPI */ @@ -223,7 +230,8 @@ compatible = "fsl,ls1012a-clockgen"; reg = <0x0 0x1ee1000 0x0 0x1000>; #clock-cells = <2>; - clocks = <&sysclk>; + clocks = <&sysclk &coreclk>; + clock-names = "sysclk", "coreclk"; }; tmu: tmu@1f00000 { |