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authorMadalin Bucur <madalin.bucur@nxp.com>2017-01-04 14:28:03 (GMT)
committerXie Xiaobo <xiaobo.xie@nxp.com>2017-07-14 09:57:28 (GMT)
commitf377053018214d5e50f904122074a1a9341e711f (patch)
tree8f7d5642b28c73fb318b00cceeff4bfb2a503c49 /arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts
parent214d1d07498e4f0e095118793df6bc6688fd0ab5 (diff)
downloadlinux-f377053018214d5e50f904122074a1a9341e711f.tar.xz
arm64: dts: ls1043: add DPAA FMan support
Add the DPAA 1.x FMan device tree nodes for LS1043A boards. Signed-off-by: Madalin Bucur <madalin.bucur@nxp.com>
Diffstat (limited to 'arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts')
-rw-r--r--arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts73
1 files changed, 73 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts
index e7446e8..c359dbb 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts
@@ -171,3 +171,76 @@
&duart1 {
status = "okay";
};
+
+#include "fsl-ls1043-post.dtsi"
+
+&fman0 {
+ ethernet@e0000 {
+ phy-handle = <&qsgmii_phy1>;
+ phy-connection-type = "qsgmii";
+ };
+
+ ethernet@e2000 {
+ phy-handle = <&qsgmii_phy2>;
+ phy-connection-type = "qsgmii";
+ };
+
+ ethernet@e4000 {
+ phy-handle = <&rgmii_phy1>;
+ phy-connection-type = "rgmii-txid";
+ };
+
+ ethernet@e6000 {
+ phy-handle = <&rgmii_phy2>;
+ phy-connection-type = "rgmii-txid";
+ };
+
+ ethernet@e8000 {
+ phy-handle = <&qsgmii_phy3>;
+ phy-connection-type = "qsgmii";
+ };
+
+ ethernet@ea000 {
+ phy-handle = <&qsgmii_phy4>;
+ phy-connection-type = "qsgmii";
+ };
+
+ ethernet@f0000 { /* 10GEC1 */
+ phy-handle = <&aqr105_phy>;
+ phy-connection-type = "xgmii";
+ };
+
+ mdio@fc000 {
+ rgmii_phy1: ethernet-phy@1 {
+ reg = <0x1>;
+ };
+
+ rgmii_phy2: ethernet-phy@2 {
+ reg = <0x2>;
+ };
+
+ qsgmii_phy1: ethernet-phy@4 {
+ reg = <0x4>;
+ };
+
+ qsgmii_phy2: ethernet-phy@5 {
+ reg = <0x5>;
+ };
+
+ qsgmii_phy3: ethernet-phy@6 {
+ reg = <0x6>;
+ };
+
+ qsgmii_phy4: ethernet-phy@7 {
+ reg = <0x7>;
+ };
+ };
+
+ mdio@fd000 {
+ aqr105_phy: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c45";
+ interrupts = <0 132 4>;
+ reg = <0x1>;
+ };
+ };
+};