Merge tag 'armsoc-dt64' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM 64-bit DT updates from Arnd Bergmann:
 "The 64-bit DT changes are surprisingly small this time, we only add
  two SoC platforms: the ZTE ZX296718 Set-top-box SoC and the SocioNext
  UniPhier LD11 TV SoC, each with their reference boards.

  There are three new machines added for existing SoC platforms:

   - The Marvell Armada 8040 development board is an impressive
     quad-core Cortex-A72 machine with three 10gbit ethernet interfaces

   - Qualcomms DragonBoard 820c single-board computer is their current
     high-end phone platform in the 96boards form factor

   - Rockchip: Tronsmart Orion r86 set-top-box is a popular mid-range
     Android box based on the 8-core rk3368 SoC"

* tag 'armsoc-dt64' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (91 commits)
  arm64: dts: berlin4ct: Add L2 cache topology
  arm64: dts: berlin4ct: enable all wdt nodes unconditionally
  arm64: dts: berlin4ct: switch to Cortex-A53 specific pmu nodes
  arm64: dts: Add ZTE ZX296718 SoC dts and Makefile
  arm64: dts: apm: Add DT node for APM X-Gene 2 CPU clocks
  arm64: dts: apm: Add X-Gene SoC hwmon to device tree
  arm64: dts: apm: Fix interrupt polarity for X-Gene PCIe legacy interrupts
  arm64: dts: apm: Add APM X-Gene v2 SoC PMU DTS entries
  arm64: dts: apm: Add APM X-Gene SoC PMU DTS entries
  arm64: dts: marvell: enable MSI for PCIe on Armada 7K/8K
  arm64: dts: ls2080a: Add 'dma-coherent' for ls2080a PCI nodes
  arm64: dts: rockchip: add Type-C phy for RK3399
  arm64: dts: rockchip: enable the gmac for rk3399 evb board
  arm64: dts: rockchip: add the gmac needed node for rk3399
  arm64: dts: rockchip: support the pmu node for rk3399
  arm64: dts: rockchip: change all interrupts cells to 4 on rk3399 SoCs
  arm64: dts: rockchip: add the tcpc for rk3399 power domain
  arm64: dts: rockchip: add efuse0 device node for rk3399
  arm64: dts: rockchip: configure PCIe support for rk3399-evb
  arm64: dts: rockchip: add the PCIe controller support for RK3399
  ...

1 files changed, 61 insertions, 0 deletions

diff --git a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
index 4f27041..17839db 100644
--- a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
@@ -262,6 +262,11 @@
 			#clock-cells = <1>;
 		};
 
+		medianoc_ade: medianoc_ade@f4520000 {
+			compatible = "syscon";
+			reg = <0x0 0xf4520000 0x0 0x4000>;
+		};
+
 		stub_clock: stub_clock {
 			compatible = "hisilicon,hi6220-stub-clk";
 			hisilicon,hi6220-clk-sram = <&sram>;
@@ -766,6 +771,7 @@
 			interrupts = <0x0 0x48 0x4>;
 			clocks = <&sys_ctrl 2>, <&sys_ctrl 1>;
 			clock-names = "ciu", "biu";
+			resets = <&sys_ctrl PERIPH_RSTDIS0_MMC0>;
 			bus-width = <0x8>;
 			vmmc-supply = <&ldo19>;
 			pinctrl-names = "default";
@@ -779,12 +785,16 @@
 			card-detect-delay = <200>;
 			hisilicon,peripheral-syscon = <&ao_ctrl>;
 			cap-sd-highspeed;
+			sd-uhs-sdr12;
+			sd-uhs-sdr25;
+			sd-uhs-sdr50;
 			reg = <0x0 0xf723e000 0x0 0x1000>;
 			interrupts = <0x0 0x49 0x4>;
 			#address-cells = <0x1>;
 			#size-cells = <0x0>;
 			clocks = <&sys_ctrl 4>, <&sys_ctrl 3>;
 			clock-names = "ciu", "biu";
+			resets = <&sys_ctrl PERIPH_RSTDIS0_MMC1>;
 			vqmmc-supply = <&ldo7>;
 			vmmc-supply = <&ldo10>;
 			bus-width = <0x4>;
@@ -802,6 +812,7 @@
 			interrupts = <0x0 0x4a 0x4>;
 			clocks = <&sys_ctrl HI6220_MMC2_CIUCLK>, <&sys_ctrl HI6220_MMC2_CLK>;
 			clock-names = "ciu", "biu";
+			resets = <&sys_ctrl PERIPH_RSTDIS0_MMC2>;
 			bus-width = <0x4>;
 			broken-cd;
 			pinctrl-names = "default", "idle";
@@ -850,5 +861,55 @@
 				};
 			};
 		};
+
+		ade: ade@f4100000 {
+			compatible = "hisilicon,hi6220-ade";
+			reg = <0x0 0xf4100000 0x0 0x7800>;
+			reg-names = "ade_base";
+			hisilicon,noc-syscon = <&medianoc_ade>;
+			resets = <&media_ctrl MEDIA_ADE>;
+			interrupts = <0 115 4>; /* ldi interrupt */
+
+			clocks = <&media_ctrl HI6220_ADE_CORE>,
+				 <&media_ctrl HI6220_CODEC_JPEG>,
+				 <&media_ctrl HI6220_ADE_PIX_SRC>;
+			/*clock name*/
+			clock-names  = "clk_ade_core",
+				       "clk_codec_jpeg",
+				       "clk_ade_pix";
+
+			assigned-clocks = <&media_ctrl HI6220_ADE_CORE>,
+				<&media_ctrl HI6220_CODEC_JPEG>;
+			assigned-clock-rates = <360000000>, <288000000>;
+			dma-coherent;
+			status = "disabled";
+
+			port {
+				ade_out: endpoint {
+					remote-endpoint = <&dsi_in>;
+				};
+			};
+		};
+
+		dsi: dsi@f4107800 {
+			compatible = "hisilicon,hi6220-dsi";
+			reg = <0x0 0xf4107800 0x0 0x100>;
+			clocks = <&media_ctrl  HI6220_DSI_PCLK>;
+			clock-names = "pclk";
+			status = "disabled";
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				/* 0 for input port */
+				port@0 {
+					reg = <0>;
+					dsi_in: endpoint {
+						remote-endpoint = <&ade_out>;
+					};
+				};
+			};
+		};
 	};
 };