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authorCaesar Wang <wxt@rock-chips.com>2016-09-05 18:17:15 (GMT)
committerHeiko Stuebner <heiko@sntech.de>2016-09-05 23:02:21 (GMT)
commit6840eb0d7646077dad813cda8b2ace08a56fd1c1 (patch)
tree57e875c3bdc873bfba104a90b286cf0e06917bd1 /arch/arm64/boot/dts/rockchip
parent210bbd38bb88989ce19208f98e530ff0468f38bd (diff)
downloadlinux-6840eb0d7646077dad813cda8b2ace08a56fd1c1.tar.xz
arm64: dts: rockchip: support the pmu node for rk3399
This patch adds to enable the ARM Performance Monitor Units for rk3399. ARM cores often have a PMU for counting cpu and cache events like cache misses and hits. This uses the new interrupt-partition mechanism to allow the two pmu instances to use the per-cpu interrupt. Signed-off-by: Caesar Wang <wxt@rock-chips.com> Acked-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Diffstat (limited to 'arch/arm64/boot/dts/rockchip')
-rw-r--r--arch/arm64/boot/dts/rockchip/rk3399.dtsi20
1 files changed, 20 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
index 529c327..8494cef 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
@@ -153,6 +153,16 @@
};
};
+ pmu_a53 {
+ compatible = "arm,cortex-a53-pmu";
+ interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster0>;
+ };
+
+ pmu_a72 {
+ compatible = "arm,cortex-a72-pmu";
+ interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster1>;
+ };
+
psci {
compatible = "arm,psci-1.0";
method = "smc";
@@ -340,6 +350,16 @@
msi-controller;
reg = <0x0 0xfee20000 0x0 0x20000>;
};
+
+ ppi-partitions {
+ ppi_cluster0: interrupt-partition-0 {
+ affinity = <&cpu_l0 &cpu_l1 &cpu_l2 &cpu_l3>;
+ };
+
+ ppi_cluster1: interrupt-partition-1 {
+ affinity = <&cpu_b0 &cpu_b1>;
+ };
+ };
};
saradc: saradc@ff100000 {