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authorMasahiro Yamada <yamada.masahiro@socionext.com>2016-06-14 03:01:42 (GMT)
committerOlof Johansson <olof@lixom.net>2016-06-14 17:40:29 (GMT)
commit1388ea2a8df4ee4c21632a048d575fa7492a8156 (patch)
tree8c4d486b00ac67b9f1c30f04543f8289176c588c /arch/arm64/boot/dts/socionext
parented6cca5f9a69cba9468ed1c467009bb12bc90287 (diff)
downloadlinux-1388ea2a8df4ee4c21632a048d575fa7492a8156.tar.xz
arm64: dts: uniphier: change cpu-release-address
At first, 256 byte of the head of DRAM space was reserved for some reasons. However, as the progress of development, it turned out unnecessary, and it was never used in the end. Move the CPU release address to leave no space. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Olof Johansson <olof@lixom.net>
Diffstat (limited to 'arch/arm64/boot/dts/socionext')
-rw-r--r--arch/arm64/boot/dts/socionext/uniphier-ph1-ld20.dtsi8
1 files changed, 4 insertions, 4 deletions
diff --git a/arch/arm64/boot/dts/socionext/uniphier-ph1-ld20.dtsi b/arch/arm64/boot/dts/socionext/uniphier-ph1-ld20.dtsi
index 31dc51b..644025c 100644
--- a/arch/arm64/boot/dts/socionext/uniphier-ph1-ld20.dtsi
+++ b/arch/arm64/boot/dts/socionext/uniphier-ph1-ld20.dtsi
@@ -77,7 +77,7 @@
compatible = "arm,cortex-a72", "arm,armv8";
reg = <0 0x000>;
enable-method = "spin-table";
- cpu-release-addr = <0 0x80000100>;
+ cpu-release-addr = <0 0x80000000>;
};
cpu1: cpu@1 {
@@ -85,7 +85,7 @@
compatible = "arm,cortex-a72", "arm,armv8";
reg = <0 0x001>;
enable-method = "spin-table";
- cpu-release-addr = <0 0x80000100>;
+ cpu-release-addr = <0 0x80000000>;
};
cpu2: cpu@100 {
@@ -93,7 +93,7 @@
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0 0x100>;
enable-method = "spin-table";
- cpu-release-addr = <0 0x80000100>;
+ cpu-release-addr = <0 0x80000000>;
};
cpu3: cpu@101 {
@@ -101,7 +101,7 @@
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0 0x101>;
enable-method = "spin-table";
- cpu-release-addr = <0 0x80000100>;
+ cpu-release-addr = <0 0x80000000>;
};
};