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| author | Yuantian Tang <andy.tang@nxp.com> | 2017-06-20 08:01:57 (GMT) |
|---|---|---|
| committer | Xie Xiaobo <xiaobo.xie@nxp.com> | 2017-09-25 07:25:43 (GMT) |
| commit | f506c916d916d5f0e4f9fdd228b61d01380338ae (patch) | |
| tree | aafedff4b23f024951659c8ff3f0ef79b5ba251b /arch/arm64/boot/dts | |
| parent | 7053b9a42f64856ec868af3a5e49ba7d4f826045 (diff) | |
| download | linux-f506c916d916d5f0e4f9fdd228b61d01380338ae.tar.xz | |
arm64: dts: ls1043a: add cpu idle support
Signed-off-by: Tang Yuantian <andy.tang@nxp.com>
Diffstat (limited to 'arch/arm64/boot/dts')
| -rw-r--r-- | arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi index d4652ee..19d48f6 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi @@ -80,6 +80,7 @@ clocks = <&clockgen 1 0>; next-level-cache = <&l2>; #cooling-cells = <2>; + cpu-idle-states = <&CPU_PH20>; }; cpu1: cpu@1 { @@ -88,6 +89,7 @@ reg = <0x1>; clocks = <&clockgen 1 0>; next-level-cache = <&l2>; + cpu-idle-states = <&CPU_PH20>; }; cpu2: cpu@2 { @@ -96,6 +98,7 @@ reg = <0x2>; clocks = <&clockgen 1 0>; next-level-cache = <&l2>; + cpu-idle-states = <&CPU_PH20>; }; cpu3: cpu@3 { @@ -104,6 +107,7 @@ reg = <0x3>; clocks = <&clockgen 1 0>; next-level-cache = <&l2>; + cpu-idle-states = <&CPU_PH20>; }; l2: l2-cache { @@ -111,6 +115,23 @@ }; }; + idle-states { + /* + * PSCI node is not added default, U-boot will add missing + * parts if it determines to use PSCI. + */ + entry-method = "arm,psci"; + + CPU_PH20: cpu-ph20 { + compatible = "arm,idle-state"; + idle-state-name = "PH20"; + arm,psci-suspend-param = <0x00010000>; + entry-latency-us = <1000>; + exit-latency-us = <1000>; + min-residency-us = <3000>; + }; + }; + memory@80000000 { device_type = "memory"; reg = <0x0 0x80000000 0 0x80000000>; |