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| author | Geert Uytterhoeven <geert+renesas@glider.be> | 2016-01-16 14:17:36 (GMT) |
|---|---|---|
| committer | Simon Horman <horms+renesas@verge.net.au> | 2016-02-05 09:43:42 (GMT) |
| commit | 7b337e61a4104d5a0abde1e733916de2208800e6 (patch) | |
| tree | e3c0ceee12a7ad506f0c3d4418051462da32f9ec /arch/arm64/boot | |
| parent | a3fc85e27b7e3c29b30909929bc64737a19fd251 (diff) | |
| download | linux-7b337e61a4104d5a0abde1e733916de2208800e6.tar.xz | |
arm64: dts: r8a7795: Add L2 cache-controller nodes
Add device nodes for the L2 caches, and link the CPU node to its L2
cache node.
The L2 cache for the Cortex-A57 CPU cores is 2 MiB large (organized as
128 KiB x 16 ways).
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Dirk Behme <dirk.behme@gmail.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Diffstat (limited to 'arch/arm64/boot')
| -rw-r--r-- | arch/arm64/boot/dts/renesas/r8a7795.dtsi | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi index 9634e3a..3f00e85 100644 --- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi @@ -39,6 +39,7 @@ compatible = "arm,cortex-a57", "arm,armv8"; reg = <0x0>; device_type = "cpu"; + next-level-cache = <&L2_CA57>; enable-method = "psci"; }; @@ -46,22 +47,29 @@ compatible = "arm,cortex-a57","arm,armv8"; reg = <0x1>; device_type = "cpu"; + next-level-cache = <&L2_CA57>; enable-method = "psci"; }; a57_2: cpu@2 { compatible = "arm,cortex-a57","arm,armv8"; reg = <0x2>; device_type = "cpu"; + next-level-cache = <&L2_CA57>; enable-method = "psci"; }; a57_3: cpu@3 { compatible = "arm,cortex-a57","arm,armv8"; reg = <0x3>; device_type = "cpu"; + next-level-cache = <&L2_CA57>; enable-method = "psci"; }; }; + L2_CA57: cache-controller@0 { + compatible = "cache"; + }; + extal_clk: extal { compatible = "fixed-clock"; #clock-cells = <0>; |