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| author | Geert Uytterhoeven <geert+renesas@glider.be> | 2015-09-30 13:22:15 (GMT) |
|---|---|---|
| committer | Simon Horman <horms+renesas@verge.net.au> | 2016-02-17 05:53:14 (GMT) |
| commit | 8e1c3aa30c2c3a5f982da9365a1ef03a3ac7a815 (patch) | |
| tree | 55f4980518428c6efe25f24bedb2d2cd9f88b1c5 /arch/arm64/boot | |
| parent | a528b4bf1a2ecb756aa65548fd5518fe82fb4648 (diff) | |
| download | linux-8e1c3aa30c2c3a5f982da9365a1ef03a3ac7a815.tar.xz | |
arm64: dts: r8a7795: Add CA53 L2 cache-controller node
Add a device node for the Cortex-A53 L2 cache-controller.
The L2 cache for the Cortex-A53 CPU cores is 512 KiB large (organized as
32 KiB x 16 ways).
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Diffstat (limited to 'arch/arm64/boot')
| -rw-r--r-- | arch/arm64/boot/dts/renesas/r8a7795.dtsi | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi index ea56066..e32b652 100644 --- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi @@ -72,6 +72,12 @@ cache-level = <2>; }; + L2_CA53: cache-controller@1 { + compatible = "cache"; + cache-unified; + cache-level = <2>; + }; + extal_clk: extal { compatible = "fixed-clock"; #clock-cells = <0>; |