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| author | Will Deacon <will.deacon@arm.com> | 2015-03-23 19:07:02 (GMT) |
|---|---|---|
| committer | Will Deacon <will.deacon@arm.com> | 2015-04-01 09:24:31 (GMT) |
| commit | 905e8c5dcaa147163672b06fe9dcb5abaacbc711 (patch) | |
| tree | 4284f6e2ecac493b6e4938e4b60e57fb521c3790 /arch/arm64/include/asm/cpufeature.h | |
| parent | cc3979b54d5f1d5b5059b404892888c304d28080 (diff) | |
| download | linux-905e8c5dcaa147163672b06fe9dcb5abaacbc711.tar.xz | |
arm64: errata: add workaround for cortex-a53 erratum #845719
When running a compat (AArch32) userspace on Cortex-A53, a load at EL0
from a virtual address that matches the bottom 32 bits of the virtual
address used by a recent load at (AArch64) EL1 might return incorrect
data.
This patch works around the issue by writing to the contextidr_el1
register on the exception return path when returning to a 32-bit task.
This workaround is patched in at runtime based on the MIDR value of the
processor.
Reviewed-by: Marc Zyngier <marc.zyngier@arm.com>
Tested-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Diffstat (limited to 'arch/arm64/include/asm/cpufeature.h')
| -rw-r--r-- | arch/arm64/include/asm/cpufeature.h | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/arch/arm64/include/asm/cpufeature.h b/arch/arm64/include/asm/cpufeature.h index 6ae35d1..82cb9f9 100644 --- a/arch/arm64/include/asm/cpufeature.h +++ b/arch/arm64/include/asm/cpufeature.h @@ -23,8 +23,9 @@ #define ARM64_WORKAROUND_CLEAN_CACHE 0 #define ARM64_WORKAROUND_DEVICE_LOAD_ACQUIRE 1 +#define ARM64_WORKAROUND_845719 2 -#define ARM64_NCAPS 2 +#define ARM64_NCAPS 3 #ifndef __ASSEMBLY__ |