diff options
author | Will Deacon <will.deacon@arm.com> | 2015-10-06 17:46:23 (GMT) |
---|---|---|
committer | Catalin Marinas <catalin.marinas@arm.com> | 2015-10-07 10:45:27 (GMT) |
commit | 8e63d38876691756f9bc6930850f1fb77809be1b (patch) | |
tree | 74f5a739675a90c71d1f07e937c2e3f512781b7e /arch/arm64/include/asm/tlbflush.h | |
parent | fa7aae8a4257e6be7051420dac1f150c1eef721b (diff) | |
download | linux-8e63d38876691756f9bc6930850f1fb77809be1b.tar.xz |
arm64: flush: use local TLB and I-cache invalidation
There are a number of places where a single CPU is running with a
private page-table and we need to perform maintenance on the TLB and
I-cache in order to ensure correctness, but do not require the operation
to be broadcast to other CPUs.
This patch adds local variants of tlb_flush_all and __flush_icache_all
to support these use-cases and updates the callers respectively.
__local_flush_icache_all also implies an isb, since it is intended to be
used synchronously.
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Acked-by: David Daney <david.daney@cavium.com>
Acked-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Diffstat (limited to 'arch/arm64/include/asm/tlbflush.h')
-rw-r--r-- | arch/arm64/include/asm/tlbflush.h | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/arch/arm64/include/asm/tlbflush.h b/arch/arm64/include/asm/tlbflush.h index 7bd2da0..96f944e 100644 --- a/arch/arm64/include/asm/tlbflush.h +++ b/arch/arm64/include/asm/tlbflush.h @@ -63,6 +63,14 @@ * only require the D-TLB to be invalidated. * - kaddr - Kernel virtual memory address */ +static inline void local_flush_tlb_all(void) +{ + dsb(nshst); + asm("tlbi vmalle1"); + dsb(nsh); + isb(); +} + static inline void flush_tlb_all(void) { dsb(ishst); |