diff options
| author | Sonic Zhang <sonic.zhang@analog.com> | 2010-09-06 10:16:04 (GMT) |
|---|---|---|
| committer | Mike Frysinger <vapier@gentoo.org> | 2010-10-22 07:48:59 (GMT) |
| commit | 99a5b2878b56d24919eb7e646f2d8e02f63a6efc (patch) | |
| tree | 5db99463ad9f68e383aa54c9d102f91f5b890091 /arch/blackfin/include | |
| parent | 73775b892ee70bdc0dbd6aeeebb50894d062f9a1 (diff) | |
| download | linux-99a5b2878b56d24919eb7e646f2d8e02f63a6efc.tar.xz | |
Blackfin: add new cacheflush syscall
Flushing caches sometimes requires anomaly workarounds which require
supervisor-only insns. Normally we don't need to flush caches from
userspace so this isn't a problem, but when gcc generates trampolines
on the stack, we do.
So add a new syscall for gcc to use modeled after the mips version.
Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Diffstat (limited to 'arch/blackfin/include')
| -rw-r--r-- | arch/blackfin/include/asm/Kbuild | 1 | ||||
| -rw-r--r-- | arch/blackfin/include/asm/cachectl.h | 20 | ||||
| -rw-r--r-- | arch/blackfin/include/asm/ptrace.h | 3 | ||||
| -rw-r--r-- | arch/blackfin/include/asm/unistd.h | 3 |
4 files changed, 26 insertions, 1 deletions
diff --git a/arch/blackfin/include/asm/Kbuild b/arch/blackfin/include/asm/Kbuild index d9eb29e..9e7c537 100644 --- a/arch/blackfin/include/asm/Kbuild +++ b/arch/blackfin/include/asm/Kbuild @@ -1,4 +1,5 @@ include include/asm-generic/Kbuild.asm header-y += bfin_sport.h +header-y += cachectl.h header-y += fixed_code.h diff --git a/arch/blackfin/include/asm/cachectl.h b/arch/blackfin/include/asm/cachectl.h new file mode 100644 index 0000000..03255df --- /dev/null +++ b/arch/blackfin/include/asm/cachectl.h @@ -0,0 +1,20 @@ +/* + * based on the mips/cachectl.h + * + * Copyright 2010 Analog Devices Inc. + * Copyright (C) 1994, 1995, 1996 by Ralf Baechle + * + * Licensed under the GPL-2 or later. + */ + +#ifndef _ASM_CACHECTL +#define _ASM_CACHECTL + +/* + * Options for cacheflush system call + */ +#define ICACHE (1<<0) /* flush instruction cache */ +#define DCACHE (1<<1) /* writeback and flush data cache */ +#define BCACHE (ICACHE|DCACHE) /* flush both caches */ + +#endif /* _ASM_CACHECTL */ diff --git a/arch/blackfin/include/asm/ptrace.h b/arch/blackfin/include/asm/ptrace.h index aaa1c6c..832d7c0 100644 --- a/arch/blackfin/include/asm/ptrace.h +++ b/arch/blackfin/include/asm/ptrace.h @@ -113,6 +113,9 @@ extern void user_disable_single_step(struct task_struct *child); /* common code demands this function */ #define ptrace_disable(child) user_disable_single_step(child) +extern int is_user_addr_valid(struct task_struct *child, + unsigned long start, unsigned long len); + /* * Get the address of the live pt_regs for the specified task. * These are saved onto the top kernel stack when the process diff --git a/arch/blackfin/include/asm/unistd.h b/arch/blackfin/include/asm/unistd.h index 14fcd25..928ae97 100644 --- a/arch/blackfin/include/asm/unistd.h +++ b/arch/blackfin/include/asm/unistd.h @@ -392,8 +392,9 @@ #define __NR_fanotify_init 371 #define __NR_fanotify_mark 372 #define __NR_prlimit64 373 +#define __NR_cacheflush 374 -#define __NR_syscall 374 +#define __NR_syscall 375 #define NR_syscalls __NR_syscall /* Old optional stuff no one actually uses */ |