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authorMike Frysinger <vapier@gentoo.org>2009-10-15 04:13:18 (GMT)
committerMike Frysinger <vapier@gentoo.org>2009-12-15 05:14:49 (GMT)
commit2abdf791151ea57f71e67136b4aaef96f534bba6 (patch)
tree74c8de46f59ec6eb985aebca29f0ca4ae903eaf8 /arch/blackfin/mach-bf533
parentcfed440997f2d02900022a3a97600f78b3b18e5b (diff)
downloadlinux-2abdf791151ea57f71e67136b4aaef96f534bba6.tar.xz
Blackfin: H8606/ip0x: drop redundant SPI ctl_reg settings
No need to set MSTR in .ctl_reg as the Blackfin SPI bus driver does this already for all parts. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Diffstat (limited to 'arch/blackfin/mach-bf533')
-rw-r--r--arch/blackfin/mach-bf533/boards/H8606.c2
-rw-r--r--arch/blackfin/mach-bf533/boards/ip0x.c14
2 files changed, 0 insertions, 16 deletions
diff --git a/arch/blackfin/mach-bf533/boards/H8606.c b/arch/blackfin/mach-bf533/boards/H8606.c
index 26a04f0..4adceb0 100644
--- a/arch/blackfin/mach-bf533/boards/H8606.c
+++ b/arch/blackfin/mach-bf533/boards/H8606.c
@@ -166,7 +166,6 @@ static struct bfin5xx_spi_chip spi_flash_chip_info = {
#if defined(CONFIG_BFIN_SPI_ADC) || defined(CONFIG_BFIN_SPI_ADC_MODULE)
/* SPI ADC chip */
static struct bfin5xx_spi_chip spi_adc_chip_info = {
- .ctl_reg = 0x1000,
.enable_dma = 1, /* use dma transfer with this chip*/
.bits_per_word = 16,
};
@@ -174,7 +173,6 @@ static struct bfin5xx_spi_chip spi_adc_chip_info = {
#if defined(CONFIG_SND_BLACKFIN_AD1836) || defined(CONFIG_SND_BLACKFIN_AD1836_MODULE)
static struct bfin5xx_spi_chip ad1836_spi_chip_info = {
- .ctl_reg = 0x1000,
.enable_dma = 0,
.bits_per_word = 16,
};
diff --git a/arch/blackfin/mach-bf533/boards/ip0x.c b/arch/blackfin/mach-bf533/boards/ip0x.c
index 644be5e..48cfbf8 100644
--- a/arch/blackfin/mach-bf533/boards/ip0x.c
+++ b/arch/blackfin/mach-bf533/boards/ip0x.c
@@ -107,20 +107,6 @@ static struct platform_device dm9000_device2 = {
#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
static struct bfin5xx_spi_chip mmc_spi_chip_info = {
-/*
- * CPOL (Clock Polarity)
- * 0 - Active high SCK
- * 1 - Active low SCK
- * CPHA (Clock Phase) Selects transfer format and operation mode
- * 0 - SCLK toggles from middle of the first data bit, slave select
- * pins controlled by hardware.
- * 1 - SCLK toggles from beginning of first data bit, slave select
- * pins controller by user software.
- * .ctl_reg = 0x1c00, * CPOL=1,CPHA=1,Sandisk 1G work
- * NO NO .ctl_reg = 0x1800, * CPOL=1,CPHA=0
- * NO NO .ctl_reg = 0x1400, * CPOL=0,CPHA=1
- */
- .ctl_reg = 0x1000, /* CPOL=0,CPHA=0,Sandisk 1G work */
.enable_dma = 0, /* if 1 - block!!! */
.bits_per_word = 8,
};