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authorMike Frysinger <vapier@gentoo.org>2010-05-27 21:47:31 (GMT)
committerMike Frysinger <vapier@gentoo.org>2010-08-06 16:55:46 (GMT)
commitdc7101bbaed644e61aa0056ff572b8d7a58e1ef0 (patch)
tree5fb562e5ab4fa556c37ea89f066c4a10cd1559e0 /arch/blackfin/mach-bf561
parent5369fba13611118bc380674a410bede0863566f2 (diff)
downloadlinux-dc7101bbaed644e61aa0056ff572b8d7a58e1ef0.tar.xz
Blackfin: update anomaly lists to latest public info
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Diffstat (limited to 'arch/blackfin/mach-bf561')
-rw-r--r--arch/blackfin/mach-bf561/include/mach/anomaly.h13
1 files changed, 9 insertions, 4 deletions
diff --git a/arch/blackfin/mach-bf561/include/mach/anomaly.h b/arch/blackfin/mach-bf561/include/mach/anomaly.h
index 5ddc981..4c108c9 100644
--- a/arch/blackfin/mach-bf561/include/mach/anomaly.h
+++ b/arch/blackfin/mach-bf561/include/mach/anomaly.h
@@ -5,7 +5,7 @@
* and can be replaced with that version at any time
* DO NOT EDIT THIS FILE
*
- * Copyright 2004-2009 Analog Devices Inc.
+ * Copyright 2004-2010 Analog Devices Inc.
* Licensed under the ADI BSD license.
* https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd
*/
@@ -152,8 +152,8 @@
#define ANOMALY_05000215 (__SILICON_REVISION__ < 5)
/* NMI Event at Boot Time Results in Unpredictable State */
#define ANOMALY_05000219 (__SILICON_REVISION__ < 5)
-/* Data Corruption with Cached External Memory and Non-Cached On-Chip L2 Memory */
-#define ANOMALY_05000220 (__SILICON_REVISION__ < 5)
+/* Data Corruption/Core Hang with L2/L3 Configured in Writeback Cache Mode */
+#define ANOMALY_05000220 (__SILICON_REVISION__ < 4)
/* Incorrect Pulse-Width of UART Start Bit */
#define ANOMALY_05000225 (__SILICON_REVISION__ < 5)
/* Scratchpad Memory Bank Reads May Return Incorrect Data */
@@ -290,10 +290,14 @@
#define ANOMALY_05000461 (1)
/* Interrupted 32-Bit SPORT Data Register Access Results In Underflow */
#define ANOMALY_05000473 (1)
-/* Core Hang With L2/L3 Configured in Writeback Cache Mode */
+/* Possible Lockup Condition whem Modifying PLL from External Memory */
#define ANOMALY_05000475 (__SILICON_REVISION__ < 4)
/* TESTSET Instruction Cannot Be Interrupted */
#define ANOMALY_05000477 (1)
+/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */
+#define ANOMALY_05000481 (1)
+/* IFLUSH sucks at life */
+#define ANOMALY_05000491 (1)
/* Anomalies that don't exist on this proc */
#define ANOMALY_05000119 (0)
@@ -319,5 +323,6 @@
#define ANOMALY_05000465 (0)
#define ANOMALY_05000467 (0)
#define ANOMALY_05000474 (0)
+#define ANOMALY_05000485 (0)
#endif