Merge branch 'for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/gerg/m68knommu

Pull m68knommu arch updates from Greg Ungerer:
 "Most of it is a cleanup of the ColdFire hardware header files.  We
  have had a few occurrances of bugs caused by inconsistent definitions
  of peripheral addresses.  These patches make them all consistent, and
  also clean out a bunch of old crap.  Overall we remove about 1000
  lines."

* 'for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/gerg/m68knommu: (27 commits)
  m68knommu: fix inconsistent formating in ColdFire 5407 definitions
  m68knommu: fix inconsistent formating in ColdFire 5307 definitions
  m68knommu: fix inconsistent formating in ColdFire 527x definitions
  m68knommu: fix inconsistent formating in ColdFire 5272 definitions
  m68knommu: fix inconsistent formating in ColdFire 523x definitions
  m68knommu: clean up ColdFire 54xx General Timer definitions
  m68knommu: clean up Pin Assignment definitions for the 54xx ColdFire CPU
  m68knommu: fix multi-function pin setup for FEC module on ColdFire 523x
  m68knommu: move ColdFire slice timer address defiens to 54xx header
  m68knommu: use read/write IO access functions in ColdFire m532x setup code
  m68knommu: modify ColdFire 532x GPIO register definitions to be consistent
  m68knommu: remove a lot of unsed definitions for 532x ColdFire
  m68knommu: use definitions for the ColdFire 528x FEC multi-function pins
  m68knommu: remove address offsets relative to IPSBAR for ColdFire 527x
  m68knommu: remove unused ColdFire 5282 register definitions
  m68knommu: fix wrong register offsets used for ColdFire 5272 multi-function pins
  m68knommu: make ColdFire 5249 MBAR2 register definitions absolute addresses
  m68knommu: make remaining ColdFire 5272 register definitions absolute addresses
  m68knommu: make ColdFire Park and Assignment register definitions absolute addresses
  m68knommu: make ColdFire Chip Select register definitions absolute addresses
  ...

1 files changed, 20 insertions, 20 deletions

diff --git a/arch/m68k/include/asm/m54xxgpt.h b/arch/m68k/include/asm/m54xxgpt.h
index df75dd8..0b69cd1 100644
--- a/arch/m68k/include/asm/m54xxgpt.h
+++ b/arch/m68k/include/asm/m54xxgpt.h
@@ -16,26 +16,26 @@
 *********************************************************************/
 
 /* Register read/write macros */
-#define MCF_GPT_GMS0       0x000800
-#define MCF_GPT_GCIR0      0x000804
-#define MCF_GPT_GPWM0      0x000808
-#define MCF_GPT_GSR0       0x00080C
-#define MCF_GPT_GMS1       0x000810
-#define MCF_GPT_GCIR1      0x000814
-#define MCF_GPT_GPWM1      0x000818
-#define MCF_GPT_GSR1       0x00081C
-#define MCF_GPT_GMS2       0x000820
-#define MCF_GPT_GCIR2      0x000824
-#define MCF_GPT_GPWM2      0x000828
-#define MCF_GPT_GSR2       0x00082C
-#define MCF_GPT_GMS3       0x000830
-#define MCF_GPT_GCIR3      0x000834
-#define MCF_GPT_GPWM3      0x000838
-#define MCF_GPT_GSR3       0x00083C
-#define MCF_GPT_GMS(x)     (0x000800+((x)*0x010))
-#define MCF_GPT_GCIR(x)    (0x000804+((x)*0x010))
-#define MCF_GPT_GPWM(x)    (0x000808+((x)*0x010))
-#define MCF_GPT_GSR(x)     (0x00080C+((x)*0x010))
+#define MCF_GPT_GMS0       (MCF_MBAR + 0x000800)
+#define MCF_GPT_GCIR0      (MCF_MBAR + 0x000804)
+#define MCF_GPT_GPWM0      (MCF_MBAR + 0x000808)
+#define MCF_GPT_GSR0       (MCF_MBAR + 0x00080C)
+#define MCF_GPT_GMS1       (MCF_MBAR + 0x000810)
+#define MCF_GPT_GCIR1      (MCF_MBAR + 0x000814)
+#define MCF_GPT_GPWM1      (MCF_MBAR + 0x000818)
+#define MCF_GPT_GSR1       (MCF_MBAR + 0x00081C)
+#define MCF_GPT_GMS2       (MCF_MBAR + 0x000820)
+#define MCF_GPT_GCIR2      (MCF_MBAR + 0x000824)
+#define MCF_GPT_GPWM2      (MCF_MBAR + 0x000828)
+#define MCF_GPT_GSR2       (MCF_MBAR + 0x00082C)
+#define MCF_GPT_GMS3       (MCF_MBAR + 0x000830)
+#define MCF_GPT_GCIR3      (MCF_MBAR + 0x000834)
+#define MCF_GPT_GPWM3      (MCF_MBAR + 0x000838)
+#define MCF_GPT_GSR3       (MCF_MBAR + 0x00083C)
+#define MCF_GPT_GMS(x)     (MCF_MBAR + 0x000800 + ((x) * 0x010))
+#define MCF_GPT_GCIR(x)    (MCF_MBAR + 0x000804 + ((x) * 0x010))
+#define MCF_GPT_GPWM(x)    (MCF_MBAR + 0x000808 + ((x) * 0x010))
+#define MCF_GPT_GSR(x)     (MCF_MBAR + 0x00080C + ((x) * 0x010))
 
 /* Bit definitions and macros for MCF_GPT_GMS */
 #define MCF_GPT_GMS_TMS(x)         (((x)&0x00000007)<<0)