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| author | Greg Ungerer <gerg@uclinux.org> | 2011-10-17 04:38:09 (GMT) |
|---|---|---|
| committer | Greg Ungerer <gerg@uclinux.org> | 2011-12-30 00:20:28 (GMT) |
| commit | ae2eca724af2802739efe02b3fc56daa8b674eb9 (patch) | |
| tree | d95406d3f1eb6c8b1ddd8641d83b86fed10dd422 /arch/m68k/mm | |
| parent | 78d705e3be4bfbd2e75157d284096d600ea6eda5 (diff) | |
| download | linux-ae2eca724af2802739efe02b3fc56daa8b674eb9.tar.xz | |
m68k: add cache support for V4e ColdFire cores running with MMU enabled
Add code to deal with instruction, data and branch caches of the V4e
ColdFire cores when they are running with the MMU enabled.
This code is loosely based on Freescales changes for the caches of the
V4e ColdFire in the 2.6.25 kernel BSP. That code was originally by
Kurt Mahan <kmahan@freescale.com> (now <kmahan@xmission.com>).
Signed-off-by: Greg Ungerer <gerg@uclinux.org>
Acked-by: Geert Uytterhoeven <geert@linux-m68k.org>
Acked-by: Matt Waddel <mwaddel@yahoo.com>
Acked-by: Kurt Mahan <kmahan@xmission.com>
Diffstat (limited to 'arch/m68k/mm')
| -rw-r--r-- | arch/m68k/mm/cache.c | 24 |
1 files changed, 21 insertions, 3 deletions
diff --git a/arch/m68k/mm/cache.c b/arch/m68k/mm/cache.c index 5437fff..95d0bf6 100644 --- a/arch/m68k/mm/cache.c +++ b/arch/m68k/mm/cache.c @@ -74,8 +74,16 @@ static unsigned long virt_to_phys_slow(unsigned long vaddr) /* RZ: use cpush %bc instead of cpush %dc, cinv %ic */ void flush_icache_range(unsigned long address, unsigned long endaddr) { - - if (CPU_IS_040_OR_060) { + if (CPU_IS_COLDFIRE) { + unsigned long start, end; + start = address & ICACHE_SET_MASK; + end = endaddr & ICACHE_SET_MASK; + if (start > end) { + flush_cf_icache(0, end); + end = ICACHE_MAX_ADDR; + } + flush_cf_icache(start, end); + } else if (CPU_IS_040_OR_060) { address &= PAGE_MASK; do { @@ -100,7 +108,17 @@ EXPORT_SYMBOL(flush_icache_range); void flush_icache_user_range(struct vm_area_struct *vma, struct page *page, unsigned long addr, int len) { - if (CPU_IS_040_OR_060) { + if (CPU_IS_COLDFIRE) { + unsigned long start, end; + start = addr & ICACHE_SET_MASK; + end = (addr + len) & ICACHE_SET_MASK; + if (start > end) { + flush_cf_icache(0, end); + end = ICACHE_MAX_ADDR; + } + flush_cf_icache(start, end); + + } else if (CPU_IS_040_OR_060) { asm volatile ("nop\n\t" ".chip 68040\n\t" "cpushp %%bc,(%0)\n\t" |