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authorLinus Torvalds <torvalds@linux-foundation.org>2013-07-06 19:39:39 (GMT)
committerLinus Torvalds <torvalds@linux-foundation.org>2013-07-06 19:39:39 (GMT)
commit7644a448ccf200d95ad4426e84a486dec5cc1703 (patch)
tree2743ee79bd0b42b96c4c2d6f7194e2e2ccfc8572 /arch/metag/kernel/cachepart.c
parent16984ce15ea43e17d964ece55ce336a8a4f40750 (diff)
parentc20eb0f1d0918c019fb2674a104e6ab59d8e62ac (diff)
downloadlinux-7644a448ccf200d95ad4426e84a486dec5cc1703.tar.xz
Merge tag 'metag-for-v3.11' of git://git.kernel.org/pub/scm/linux/kernel/git/jhogan/metag
Pull Metag architecture changes from James Hogan: - Infrastructure and DT files for TZ1090 SoC (pin control drivers already merged via pinctrl tree). - Panic on boot instead of just warning if cache aliasing possible. - Various SMP/hotplug fixes. - Various other randconfig/sparse fixes. * tag 'metag-for-v3.11' of git://git.kernel.org/pub/scm/linux/kernel/git/jhogan/metag: (24 commits) metag: move EXPORT_SYMBOL(csum_partial) to metag_ksyms.c metag: cpu hotplug: route_irq: preserve irq mask metag: kick: add missing irq_enter/exit to kick_handler() metag: smp: don't spin waiting for CPU to start metag: smp: enable irqs after set_cpu_online metag: use clear_tasks_mm_cpumask() metag: tz1090: select and instantiate pinctrl-tz1090-pdc metag: tz1090: select and instantiate pinctrl-tz1090 metag: don't check for cache aliasing on smp cpu boot metag: panic if cache aliasing possible metag: *.dts: include using preprocessor metag: add <dt-bindings/> symlink metag/.gitignore: Extend the *.dtb pattern to match the dtb.S files metag/traps: include setup.h for the per_cpu_trap_init declaration metag/traps: Mark die() as __noreturn to match the declaration. metag/processor.h: Add missing cpuinfo_op declaration. metag/setup: Restrict scope for the capabilities variable metag/mm/cache: Restrict scope for metag_lnkget_probe metag/asm/irq.h: Declare init_IRQ metag/kernel/irq.c: Declare root_domain as static ...
Diffstat (limited to 'arch/metag/kernel/cachepart.c')
-rw-r--r--arch/metag/kernel/cachepart.c13
1 files changed, 7 insertions, 6 deletions
diff --git a/arch/metag/kernel/cachepart.c b/arch/metag/kernel/cachepart.c
index 954548b..0a2385f 100644
--- a/arch/metag/kernel/cachepart.c
+++ b/arch/metag/kernel/cachepart.c
@@ -100,22 +100,23 @@ void check_for_cache_aliasing(int thread_id)
thread_cache_size =
get_thread_cache_size(cache_type, thread_id);
if (thread_cache_size < 0)
- pr_emerg("Can't read %s cache size", \
+ pr_emerg("Can't read %s cache size\n",
cache_type ? "DCACHE" : "ICACHE");
else if (thread_cache_size == 0)
/* Cache is off. No need to check for aliasing */
continue;
if (thread_cache_size / CACHE_ASSOCIATIVITY > PAGE_SIZE) {
- pr_emerg("Cache aliasing detected in %s on Thread %d",
+ pr_emerg("Potential cache aliasing detected in %s on Thread %d\n",
cache_type ? "DCACHE" : "ICACHE", thread_id);
- pr_warn("Total %s size: %u bytes",
- cache_type ? "DCACHE" : "ICACHE ",
+ pr_warn("Total %s size: %u bytes\n",
+ cache_type ? "DCACHE" : "ICACHE",
cache_type ? get_dcache_size()
: get_icache_size());
- pr_warn("Thread %s size: %d bytes",
+ pr_warn("Thread %s size: %d bytes\n",
cache_type ? "CACHE" : "ICACHE",
thread_cache_size);
- pr_warn("Page Size: %lu bytes", PAGE_SIZE);
+ pr_warn("Page Size: %lu bytes\n", PAGE_SIZE);
+ panic("Potential cache aliasing detected");
}
}
}