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| author | Douglas Leung <douglas@mips.com> | 2012-07-19 07:11:13 (GMT) |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2012-07-19 09:23:43 (GMT) |
| commit | dc34b05fea0cc9a869863b929f37f1e8ce30edf4 (patch) | |
| tree | ad064e7dcf5235d8c51060ed0c8db167c5490bd3 /arch/mips/kernel/octeon_switch.S | |
| parent | c022630633624a75b3b58f43dd3c6cc896a56cff (diff) | |
| download | linux-dc34b05fea0cc9a869863b929f37f1e8ce30edf4.tar.xz | |
MIPS: Fix decoding of c0_config1 for MIPSxx caches with 32 ways per set.
This affects certain 4Kc cores.
Signed-off-by: Douglas Leung <douglas@mips.com>
Signed-off-by: Steven J. Hill <sjhill@mips.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/3855/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/kernel/octeon_switch.S')
0 files changed, 0 insertions, 0 deletions