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author | John Crispin <blogic@openwrt.org> | 2013-01-19 08:54:24 (GMT) |
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committer | John Crispin <blogic@openwrt.org> | 2013-02-16 23:15:17 (GMT) |
commit | 740c606e8e79c3e3800afbc32b4e6123da403d6c (patch) | |
tree | d8fad6b56dcdcdfba522011bab2e114d221ba6a3 /arch/mips/lantiq/clk.c | |
parent | 3d18c17e4f1699c3a4f47d2483c5d4c3ab3a242b (diff) | |
download | linux-740c606e8e79c3e3800afbc32b4e6123da403d6c.tar.xz |
MIPS: lantiq: adds static clock for PP32
The Lantiq DSL SoCs have an internal networking processor. Add code to read
the static clock rate.
Signed-off-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/4815/
Diffstat (limited to 'arch/mips/lantiq/clk.c')
-rw-r--r-- | arch/mips/lantiq/clk.c | 12 |
1 files changed, 10 insertions, 2 deletions
diff --git a/arch/mips/lantiq/clk.c b/arch/mips/lantiq/clk.c index ce2f129..d903560 100644 --- a/arch/mips/lantiq/clk.c +++ b/arch/mips/lantiq/clk.c @@ -26,13 +26,15 @@ #include "prom.h" /* lantiq socs have 3 static clocks */ -static struct clk cpu_clk_generic[3]; +static struct clk cpu_clk_generic[4]; -void clkdev_add_static(unsigned long cpu, unsigned long fpi, unsigned long io) +void clkdev_add_static(unsigned long cpu, unsigned long fpi, + unsigned long io, unsigned long ppe) { cpu_clk_generic[0].rate = cpu; cpu_clk_generic[1].rate = fpi; cpu_clk_generic[2].rate = io; + cpu_clk_generic[3].rate = ppe; } struct clk *clk_get_cpu(void) @@ -51,6 +53,12 @@ struct clk *clk_get_io(void) return &cpu_clk_generic[2]; } +struct clk *clk_get_ppe(void) +{ + return &cpu_clk_generic[3]; +} +EXPORT_SYMBOL_GPL(clk_get_ppe); + static inline int clk_good(struct clk *clk) { return clk && !IS_ERR(clk); |