diff options
| author | Ralf Baechle <ralf@linux-mips.org> | 2005-12-08 13:00:20 (GMT) |
|---|---|---|
| committer | <ralf@denk.linux-mips.net> | 2006-01-10 13:39:06 (GMT) |
| commit | e7958bb90d57f0da073cbd031a1808de51d1de15 (patch) | |
| tree | b4f0d57ab157c64ce23722dbd29864901794a019 /arch/mips/mm/c-r4k.c | |
| parent | 571e0bed85470882cedfb100e847902911c3f4d2 (diff) | |
| download | linux-e7958bb90d57f0da073cbd031a1808de51d1de15.tar.xz | |
MIPS: Rename MIPS_CPU_ISA_M{32,64} -> MIPS_CPU_ISA_M{32,64}R1.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/mm/c-r4k.c')
| -rw-r--r-- | arch/mips/mm/c-r4k.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c index 38223b4..422b55f 100644 --- a/arch/mips/mm/c-r4k.c +++ b/arch/mips/mm/c-r4k.c @@ -1183,8 +1183,8 @@ static void __init setup_scache(void) if (!sc_present) return; - if ((c->isa_level == MIPS_CPU_ISA_M32 || - c->isa_level == MIPS_CPU_ISA_M64) && + if ((c->isa_level == MIPS_CPU_ISA_M32R1 || + c->isa_level == MIPS_CPU_ISA_M64R1) && !(c->scache.flags & MIPS_CACHE_NOT_PRESENT)) panic("Dunno how to handle MIPS32 / MIPS64 second level cache"); |