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authorFlorian Fainelli <f.fainelli@gmail.com>2016-04-04 17:55:34 (GMT)
committerRalf Baechle <ralf@linux-mips.org>2016-05-13 12:02:06 (GMT)
commitc130d2fd3d59fbd5d269f7d5827bd4ed1d94aec6 (patch)
tree71d712381550ab25f5209f464a7a6ab1f19182bd /arch/mips/mm
parent0201bfb1af4747f3642fa7a707fd81bbf78390b7 (diff)
downloadlinux-c130d2fd3d59fbd5d269f7d5827bd4ed1d94aec6.tar.xz
MIPS: BMIPS: BMIPS5000 has I cache filing from D cache
BMIPS5000 and BMIPS52000 processors have their I-cache filling from the D-cache. Since BMIPS_GENERIC does not provide (yet) a cpu-feature-overrides.h file, this was not set anywhere, so make sure the R4K cache detection takes care of that. Fixes: d74b0172e4e2c ("MIPS: BMIPS: Add special cache handling in c-r4k.c") Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/13010/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/mm')
-rw-r--r--arch/mips/mm/c-r4k.c4
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index e64d595..92e54fb 100644
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -1317,6 +1317,10 @@ static void probe_pcache(void)
c->icache.flags |= MIPS_CACHE_IC_F_DC;
break;
+ case CPU_BMIPS5000:
+ c->icache.flags |= MIPS_CACHE_IC_F_DC;
+ break;
+
case CPU_LOONGSON2:
/*
* LOONGSON2 has 4 way icache, but when using indexed cache op,