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| author | Maciej W. Rozycki <macro@linux-mips.org> | 2013-09-17 15:58:10 (GMT) |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2013-09-18 18:25:19 (GMT) |
| commit | 8ff374b9c296b96484d5e63b45b22d0862ffee8f (patch) | |
| tree | 0a40c8b881b985854a58793b14ca7b4de9c6f123 /arch/mips/mti-sead3 | |
| parent | b42b4f3af8b1ac2f7b09781d523bf918f366d8d6 (diff) | |
| download | linux-8ff374b9c296b96484d5e63b45b22d0862ffee8f.tar.xz | |
MIPS: Cleanup CP0 PRId and CP1 FPIR register access masks
Replace hardcoded CP0 PRId and CP1 FPIR register access masks throughout.
The change does not touch places that use shifted or partial masks.
Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/5838/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/mti-sead3')
| -rw-r--r-- | arch/mips/mti-sead3/sead3-time.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/arch/mips/mti-sead3/sead3-time.c b/arch/mips/mti-sead3/sead3-time.c index a43ea3c..552d26c 100644 --- a/arch/mips/mti-sead3/sead3-time.c +++ b/arch/mips/mti-sead3/sead3-time.c @@ -7,6 +7,7 @@ */ #include <linux/init.h> +#include <asm/cpu.h> #include <asm/setup.h> #include <asm/time.h> #include <asm/irq.h> @@ -34,7 +35,7 @@ static void __iomem *status_reg = (void __iomem *)0xbf000410; */ static unsigned int __init estimate_cpu_frequency(void) { - unsigned int prid = read_c0_prid() & 0xffff00; + unsigned int prid = read_c0_prid() & (PRID_COMP_MASK | PRID_IMP_MASK); unsigned int tick = 0; unsigned int freq; unsigned int orig; |