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authorPaul Burton <paul.burton@imgtec.com>2016-05-17 14:31:06 (GMT)
committerRalf Baechle <ralf@linux-mips.org>2016-05-28 10:35:03 (GMT)
commitba01cf0e1244fc3e4a24b4a111148c0d70025b36 (patch)
tree1535064a6b8b401193e06add5dcabca8f6b7a1d5 /arch/mips/sgi-ip32
parentd642e4e7b42f379fb9383ef1505f9d67895fb815 (diff)
downloadlinux-ba01cf0e1244fc3e4a24b4a111148c0d70025b36.tar.xz
irqchip: mips-gic: Setup EIC mode on each CPU if it's in use
When EIC mode is in use (cpu_has_veic is true) enable it on each CPU during GIC initialisation. Otherwise there may be a mismatch between the hardware default interrupt model & that expected by the kernel. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Reviewed-by: Matt Redfearn <matt.redfearn@imgtec.com> Tested-by: Matt Redfearn <matt.redfearn@imgtec.com> Acked-by: Thomas Gleixner <tglx@linutronix.de> Cc: Paul Burton <paul.burton@imgtec.com> Cc: Marc Zyngier <marc.zyngier@arm.com> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: linux-kernel@vger.kernel.org Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/13274/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/sgi-ip32')
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