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| author | Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> | 2013-12-13 15:42:19 (GMT) |
|---|---|---|
| committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2013-12-29 12:32:47 (GMT) |
| commit | e68f31f4520ea5d1ddbcaddb320ef0b4201eef3c (patch) | |
| tree | ab66c89f6347e23dea8ded7334ca2ef691c099fd /arch/openrisc | |
| parent | 017f161a55b48807a73fc9dff0b69f081bf43ee3 (diff) | |
| download | linux-e68f31f4520ea5d1ddbcaddb320ef0b4201eef3c.tar.xz | |
ARM: 7922/1: l2x0: add Marvell Tauros3 support
This adds support for the Marvell Tauros3 cache controller which
is compatible with pl310 cache controller but broadcasts L1 cache
operations to L2 cache. While updating the binding documentation,
clean up the list of possible compatibles. Also reorder driver
compatibles to allow non-ARM derivated to be compatible to ARM
cache controller compatibles.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Reviewed-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/openrisc')
0 files changed, 0 insertions, 0 deletions