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authorLinus Torvalds <torvalds@linux-foundation.org>2016-01-17 21:20:54 (GMT)
committerLinus Torvalds <torvalds@linux-foundation.org>2016-01-17 21:20:54 (GMT)
commita4eff16c54886c11972d6396ce8447b99e097343 (patch)
treeeae80ceb9c2827946f31e4bddc6f9c3a9da7b17a /arch/parisc/kernel/pci.c
parent0cbeafb245ca568bc0765645aa64f0451b716657 (diff)
parentb0e551313ebde17764f3a5ed273df524d1e7e690 (diff)
downloadlinux-a4eff16c54886c11972d6396ce8447b99e097343.tar.xz
Merge branch 'parisc-4.5-1' of git://git.kernel.org/pub/scm/linux/kernel/git/deller/parisc-linux
Pull parsic updates from Helge Deller: "This patchset includes two major fixes which are both scheduled for stable: First, __ARCH_SI_PREAMBLE_SIZE was defined with a wrong value. Second, huge page pte and TLB changes needed protection with a spinlock. Other than that there are just some trivial optimizations and cleanups" * 'parisc-4.5-1' of git://git.kernel.org/pub/scm/linux/kernel/git/deller/parisc-linux: parisc: Protect huge page pte changes with spinlocks parisc: Imporove debug info about space registers and TLB configuration parisc: Drop parisc-specific NSIGTRAP define parisc: Fix __ARCH_SI_PREAMBLE_SIZE parisc: Reduce overhead of parisc_requires_coherency() parisc: Initialize PCI bridge cache line and default latency
Diffstat (limited to 'arch/parisc/kernel/pci.c')
-rw-r--r--arch/parisc/kernel/pci.c26
1 files changed, 26 insertions, 0 deletions
diff --git a/arch/parisc/kernel/pci.c b/arch/parisc/kernel/pci.c
index c99f3dd..0903c6a 100644
--- a/arch/parisc/kernel/pci.c
+++ b/arch/parisc/kernel/pci.c
@@ -170,6 +170,32 @@ void pcibios_set_master(struct pci_dev *dev)
(0x80 << 8) | pci_cache_line_size);
}
+/*
+ * pcibios_init_bridge() initializes cache line and default latency
+ * for pci controllers and pci-pci bridges
+ */
+void __init pcibios_init_bridge(struct pci_dev *dev)
+{
+ unsigned short bridge_ctl, bridge_ctl_new;
+
+ /* We deal only with pci controllers and pci-pci bridges. */
+ if (!dev || (dev->class >> 8) != PCI_CLASS_BRIDGE_PCI)
+ return;
+
+ /* PCI-PCI bridge - set the cache line and default latency
+ * (32) for primary and secondary buses.
+ */
+ pci_write_config_byte(dev, PCI_SEC_LATENCY_TIMER, 32);
+
+ pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &bridge_ctl);
+
+ bridge_ctl_new = bridge_ctl | PCI_BRIDGE_CTL_PARITY |
+ PCI_BRIDGE_CTL_SERR | PCI_BRIDGE_CTL_MASTER_ABORT;
+ dev_info(&dev->dev, "Changing bridge control from 0x%08x to 0x%08x\n",
+ bridge_ctl, bridge_ctl_new);
+
+ pci_write_config_word(dev, PCI_BRIDGE_CONTROL, bridge_ctl_new);
+}
/*
* pcibios align resources() is called every time generic PCI code