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| author | Kumar Gala <galak@kernel.crashing.org> | 2008-05-30 18:43:43 (GMT) |
|---|---|---|
| committer | Kumar Gala <galak@kernel.crashing.org> | 2008-06-02 19:44:25 (GMT) |
| commit | c054065bc10a7ee2bcf78b5bc95f4b4d9bdc923a (patch) | |
| tree | 023b60c1b55c04c2db08983a3aaef151d081fcac /arch/powerpc/boot/dts/mpc8548cds.dts | |
| parent | acd4b715ec83e451990bb82bdbf28ecaeab1b67d (diff) | |
| download | linux-c054065bc10a7ee2bcf78b5bc95f4b4d9bdc923a.tar.xz | |
[POWERPC] 85xx: Add next-level-cache property
Added next-level-cache to the L1 and a reference to the new L2 label.
This is per the ePAPR 0.94 spec. Since we are't really dependent on this
today we aren't supporting the "legacy" l2-cache phandle that is specified
in the PPC v2.1 OF Binding spec.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'arch/powerpc/boot/dts/mpc8548cds.dts')
| -rw-r--r-- | arch/powerpc/boot/dts/mpc8548cds.dts | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/arch/powerpc/boot/dts/mpc8548cds.dts b/arch/powerpc/boot/dts/mpc8548cds.dts index 213c88e..205598d 100644 --- a/arch/powerpc/boot/dts/mpc8548cds.dts +++ b/arch/powerpc/boot/dts/mpc8548cds.dts @@ -45,6 +45,7 @@ timebase-frequency = <0>; // 33 MHz, from uboot bus-frequency = <0>; // 166 MHz clock-frequency = <0>; // 825 MHz, from uboot + next-level-cache = <&L2>; }; }; @@ -68,7 +69,7 @@ interrupts = <18 2>; }; - l2-cache-controller@20000 { + L2: l2-cache-controller@20000 { compatible = "fsl,8548-l2-cache-controller"; reg = <0x20000 0x1000>; cache-line-size = <32>; // 32 bytes |