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authorZhao Chenhui <chenhui.zhao@freescale.com>2012-07-20 12:42:35 (GMT)
committerKumar Gala <galak@kernel.crashing.org>2012-09-12 19:57:08 (GMT)
commitbf34526374a334ddfafaed73b0d8bf7eb4dea833 (patch)
tree409a950552f72205381e9ecad3bb8cd02d5f4b93 /arch/powerpc/include/asm
parentae5cab476342bc7311945cf89d5cbd8d57f4a5a9 (diff)
downloadlinux-bf34526374a334ddfafaed73b0d8bf7eb4dea833.tar.xz
powerpc/85xx: implement hardware timebase sync
Do hardware timebase sync. Firstly, stop all timebases, and transfer the timebase value of the boot core to the other core. Finally, start all timebases. Only apply to dual-core chips, such as MPC8572, P2020, etc. Signed-off-by: Zhao Chenhui <chenhui.zhao@freescale.com> Signed-off-by: Li Yang <leoli@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'arch/powerpc/include/asm')
-rw-r--r--arch/powerpc/include/asm/fsl_guts.h2
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/powerpc/include/asm/fsl_guts.h b/arch/powerpc/include/asm/fsl_guts.h
index aa4c488..dd5ba2c 100644
--- a/arch/powerpc/include/asm/fsl_guts.h
+++ b/arch/powerpc/include/asm/fsl_guts.h
@@ -48,6 +48,8 @@ struct ccsr_guts {
__be32 dmuxcr; /* 0x.0068 - DMA Mux Control Register */
u8 res06c[0x70 - 0x6c];
__be32 devdisr; /* 0x.0070 - Device Disable Control */
+#define CCSR_GUTS_DEVDISR_TB1 0x00001000
+#define CCSR_GUTS_DEVDISR_TB0 0x00004000
__be32 devdisr2; /* 0x.0074 - Device Disable Control 2 */
u8 res078[0x7c - 0x78];
__be32 pmjcr; /* 0x.007c - 4 Power Management Jog Control Register */