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| author | Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com> | 2016-07-13 09:35:21 (GMT) |
|---|---|---|
| committer | Michael Ellerman <mpe@ellerman.id.au> | 2016-07-17 06:42:50 (GMT) |
| commit | bf16cdf48a5369ba29614a0ade4ae5daf7a9e47c (patch) | |
| tree | 4abc3ff7bb6e15944e9a377bfe4a6064b457a402 /arch/powerpc/include | |
| parent | 8cd6d3c23e226ec6cb8825e1aa6a391ebda71c72 (diff) | |
| download | linux-bf16cdf48a5369ba29614a0ade4ae5daf7a9e47c.tar.xz | |
powerpc/mm/radix: Update LPCR HR bit as per ISA
PowerISA 3.0 requires the MMU mode (radix vs. hash) of the hypervisor
to be mirrored in the LPCR register, in addition to the partition table.
This is done to avoid fetching from the table when deciding, among other
things, how to perform transitions to HV mode on some interrupts.
So let's set it up appropriately
Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
Acked-by: Balbir Singh <bsingharora@gmail.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Diffstat (limited to 'arch/powerpc/include')
| -rw-r--r-- | arch/powerpc/include/asm/reg.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h index 6de6abe..295a19a 100644 --- a/arch/powerpc/include/asm/reg.h +++ b/arch/powerpc/include/asm/reg.h @@ -366,6 +366,7 @@ #define LPCR_HVICE 0x00000002 /* P9: HV interrupt enable */ #define LPCR_HDICE 0x00000001 /* Hyp Decr enable (HV,PR,EE) */ #define LPCR_UPRT 0x00400000 /* Use Process Table (ISA 3) */ +#define LPCR_HR 0x00100000 #ifndef SPRN_LPID #define SPRN_LPID 0x13F /* Logical Partition Identifier */ #endif |