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| author | Kumar Gala <galak@kernel.crashing.org> | 2009-10-16 23:48:40 (GMT) |
|---|---|---|
| committer | Kumar Gala <galak@kernel.crashing.org> | 2010-10-14 05:55:14 (GMT) |
| commit | 55fd766b5fad8240b7a6e994b5779a46d28f73d4 (patch) | |
| tree | d00d9ddd5fb635d083e573d68675115489c46f19 /arch/powerpc/mm/Makefile | |
| parent | 988cf86d4f0da4150e808300c145ba87c0aad02f (diff) | |
| download | linux-55fd766b5fad8240b7a6e994b5779a46d28f73d4.tar.xz | |
powerpc/fsl-booke64: Use TLB CAMs to cover linear mapping on FSL 64-bit chips
On Freescale parts typically have TLB array for large mappings that we can
bolt the linear mapping into. We utilize the code that already exists
on PPC32 on the 64-bit side to setup the linear mapping to be cover by
bolted TLB entries. We utilize a quarter of the variable size TLB array
for this purpose.
Additionally, we limit the amount of memory to what we can cover via
bolted entries so we don't get secondary faults in the TLB miss
handlers. We should fix this limitation in the future.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'arch/powerpc/mm/Makefile')
| -rw-r--r-- | arch/powerpc/mm/Makefile | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/powerpc/mm/Makefile b/arch/powerpc/mm/Makefile index 53102f3..bdca46e 100644 --- a/arch/powerpc/mm/Makefile +++ b/arch/powerpc/mm/Makefile @@ -23,7 +23,7 @@ obj-$(CONFIG_PPC_STD_MMU) += hash_low_$(CONFIG_WORD_SIZE).o \ mmu_context_hash$(CONFIG_WORD_SIZE).o obj-$(CONFIG_40x) += 40x_mmu.o obj-$(CONFIG_44x) += 44x_mmu.o -obj-$(CONFIG_FSL_BOOKE) += fsl_booke_mmu.o +obj-$(CONFIG_PPC_FSL_BOOK3E) += fsl_booke_mmu.o obj-$(CONFIG_NEED_MULTIPLE_NODES) += numa.o obj-$(CONFIG_PPC_MM_SLICES) += slice.o ifeq ($(CONFIG_HUGETLB_PAGE),y) |