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authorAnton Blanchard <anton@samba.org>2015-07-07 03:56:59 (GMT)
committerMichael Ellerman <mpe@ellerman.id.au>2015-07-13 05:47:28 (GMT)
commit1c53973172f84fafa8ad94f17ac427fdd4f260a2 (patch)
tree978a7c6fe05e7c8366a1fad207535173733f2a46 /arch/powerpc
parente8a4fd0afe05d5213d809fa686d3b8319464acfd (diff)
downloadlinux-1c53973172f84fafa8ad94f17ac427fdd4f260a2.tar.xz
powerpc: Remove mtmsrd(), use existing mtmsr()
mtmsr() does the right thing on 32bit and 64bit, so use it everywhere. Signed-off-by: Anton Blanchard <anton@samba.org> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Diffstat (limited to 'arch/powerpc')
-rw-r--r--arch/powerpc/include/asm/reg.h3
-rw-r--r--arch/powerpc/oprofile/op_model_power4.c4
2 files changed, 3 insertions, 4 deletions
diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h
index af56b5c..bb27588 100644
--- a/arch/powerpc/include/asm/reg.h
+++ b/arch/powerpc/include/asm/reg.h
@@ -1193,8 +1193,7 @@
#ifdef CONFIG_PPC_BOOK3S_64
#define __mtmsrd(v, l) asm volatile("mtmsrd %0," __stringify(l) \
: : "r" (v) : "memory")
-#define mtmsrd(v) __mtmsrd((v), 0)
-#define mtmsr(v) mtmsrd(v)
+#define mtmsr(v) __mtmsrd((v), 0)
#else
#define mtmsr(v) asm volatile("mtmsr %0" : \
: "r" ((unsigned long)(v)) \
diff --git a/arch/powerpc/oprofile/op_model_power4.c b/arch/powerpc/oprofile/op_model_power4.c
index 962fe7b..4b32e94 100644
--- a/arch/powerpc/oprofile/op_model_power4.c
+++ b/arch/powerpc/oprofile/op_model_power4.c
@@ -207,7 +207,7 @@ static int power4_start(struct op_counter_config *ctr)
unsigned int mmcr0;
/* set the PMM bit (see comment below) */
- mtmsrd(mfmsr() | MSR_PMM);
+ mtmsr(mfmsr() | MSR_PMM);
for (i = 0; i < cur_cpu_spec->num_pmcs; ++i) {
if (ctr[i].enabled) {
@@ -377,7 +377,7 @@ static void power4_handle_interrupt(struct pt_regs *regs,
is_kernel = get_kernel(pc, mmcra);
/* set the PMM bit (see comment below) */
- mtmsrd(mfmsr() | MSR_PMM);
+ mtmsr(mfmsr() | MSR_PMM);
/* Check that the SIAR valid bit in MMCRA is set to 1. */
if ((mmcra & MMCRA_SIAR_VALID_MASK) == MMCRA_SIAR_VALID_MASK)