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authorHeiko Carstens <heiko.carstens@de.ibm.com>2016-12-28 10:33:48 (GMT)
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>2017-07-05 12:40:26 (GMT)
commit0e9867b7113c56b367f2e753cd411cf7cef0d2ec (patch)
treeb0a67b38e4ef9cd65428dac0a092712a841c9306 /arch/s390
parent9d00195bc0afa0252b9cdb157eb4ed1e13631bc6 (diff)
downloadlinux-0e9867b7113c56b367f2e753cd411cf7cef0d2ec.tar.xz
s390/ctl_reg: make __ctl_load a full memory barrier
[ Upstream commit e991c24d68b8c0ba297eeb7af80b1e398e98c33f ] We have quite a lot of code that depends on the order of the __ctl_load inline assemby and subsequent memory accesses, like e.g. disabling lowcore protection and the writing to lowcore. Since the __ctl_load macro does not have memory barrier semantics, nor any other dependencies the compiler is, theoretically, free to shuffle code around. Or in other words: storing to lowcore could happen before lowcore protection is disabled. In order to avoid this class of potential bugs simply add a full memory barrier to the __ctl_load macro. Signed-off-by: Heiko Carstens <heiko.carstens@de.ibm.com> Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com> Signed-off-by: Sasha Levin <alexander.levin@verizon.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'arch/s390')
-rw-r--r--arch/s390/include/asm/ctl_reg.h4
1 files changed, 3 insertions, 1 deletions
diff --git a/arch/s390/include/asm/ctl_reg.h b/arch/s390/include/asm/ctl_reg.h
index d7697ab..8e136b8 100644
--- a/arch/s390/include/asm/ctl_reg.h
+++ b/arch/s390/include/asm/ctl_reg.h
@@ -15,7 +15,9 @@
BUILD_BUG_ON(sizeof(addrtype) != (high - low + 1) * sizeof(long));\
asm volatile( \
" lctlg %1,%2,%0\n" \
- : : "Q" (*(addrtype *)(&array)), "i" (low), "i" (high));\
+ : \
+ : "Q" (*(addrtype *)(&array)), "i" (low), "i" (high) \
+ : "memory"); \
}
#define __ctl_store(array, low, high) { \