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authorPaul Mundt <lethal@linux-sh.org>2010-10-13 23:44:55 (GMT)
committerPaul Mundt <lethal@linux-sh.org>2010-10-13 23:44:55 (GMT)
commitb6b77b2d5ffd2f8ee74fcc27661f7f4962c34705 (patch)
treec4596337ce521cd5be2f96af85ccbe88b76c4d80 /arch/sh/drivers
parent61a46766c9d5d8fb5dad23da1b7cc4cb8b0107da (diff)
downloadlinux-b6b77b2d5ffd2f8ee74fcc27661f7f4962c34705.tar.xz
sh: pci: Support secondary FPGA-driven PCIe clocks on SDK7786.
The SDK7786 FPGA has secondary control over the PCIe clocks, specifically relating to the slots and oscillator. This ties the FPGA clocks in to the clock framework and balances the refcounting similar to how the primary on-chip clocks are managed. While the on-chip clocks are per-port, the FPGA clock enable/disable is global for the entire block. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'arch/sh/drivers')
-rw-r--r--arch/sh/drivers/pci/fixups-sdk7786.c1
-rw-r--r--arch/sh/drivers/pci/pcie-sh7786.c23
2 files changed, 21 insertions, 3 deletions
diff --git a/arch/sh/drivers/pci/fixups-sdk7786.c b/arch/sh/drivers/pci/fixups-sdk7786.c
index 058a65a..0e18ee3 100644
--- a/arch/sh/drivers/pci/fixups-sdk7786.c
+++ b/arch/sh/drivers/pci/fixups-sdk7786.c
@@ -10,7 +10,6 @@
#define pr_fmt(fmt) "PCI: " fmt
#include <linux/init.h>
-#include <linux/clk.h>
#include <linux/kernel.h>
#include <linux/pci.h>
#include <mach/fpga.h>
diff --git a/arch/sh/drivers/pci/pcie-sh7786.c b/arch/sh/drivers/pci/pcie-sh7786.c
index 8ec4af1..ae0b2c9 100644
--- a/arch/sh/drivers/pci/pcie-sh7786.c
+++ b/arch/sh/drivers/pci/pcie-sh7786.c
@@ -17,7 +17,6 @@
#include <linux/sh_clk.h>
#include "pcie-sh7786.h"
#include <asm/sizes.h>
-#include <asm/clock.h>
struct sh7786_pcie_port {
struct pci_channel *hose;
@@ -510,6 +509,7 @@ static struct sh7786_pcie_hwops sh7786_65nm_pcie_hwops __initdata = {
static int __init sh7786_pcie_init(void)
{
+ struct clk *platclk;
int ret = 0, i;
printk(KERN_NOTICE "PCI: Starting initialization.\n");
@@ -527,6 +527,22 @@ static int __init sh7786_pcie_init(void)
if (unlikely(!sh7786_pcie_ports))
return -ENOMEM;
+ /*
+ * Fetch any optional platform clock associated with this block.
+ *
+ * This is a rather nasty hack for boards with spec-mocking FPGAs
+ * that have a secondary set of clocks outside of the on-chip
+ * ones that need to be accounted for before there is any chance
+ * of touching the existing MSTP bits or CPG clocks.
+ */
+ platclk = clk_get(NULL, "pcie_plat_clk");
+ if (IS_ERR(platclk)) {
+ /* Sane hardware should probably get a WARN_ON.. */
+ platclk = NULL;
+ }
+
+ clk_enable(platclk);
+
printk(KERN_NOTICE "PCI: probing %d ports.\n", nr_ports);
for (i = 0; i < nr_ports; i++) {
@@ -539,8 +555,11 @@ static int __init sh7786_pcie_init(void)
ret |= sh7786_pcie_hwops->port_init_hw(port);
}
- if (unlikely(ret))
+ if (unlikely(ret)) {
+ clk_disable(platclk);
+ clk_put(platclk);
return ret;
+ }
return 0;
}