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| author | Rich Felker <dalias@libc.org> | 2016-03-17 23:09:37 (GMT) |
|---|---|---|
| committer | Rich Felker <dalias@libc.org> | 2016-08-05 03:29:31 (GMT) |
| commit | 5a846abad07f6f30adfa3e46c5c7a47d2e7b1e63 (patch) | |
| tree | fc16a7c8f74a2010f0134ef3e69d20fde929bc08 /arch/sh/mm/cache.c | |
| parent | 03767daa1387f87619404bfe108ebb6aa5826e00 (diff) | |
| download | linux-5a846abad07f6f30adfa3e46c5c7a47d2e7b1e63.tar.xz | |
sh: add support for J-Core J2 processor
At the CPU/ISA level, the J2 is compatible with SH-2, and thus the
changes to add J2 support build on existing SH-2 support. However, J2
does not duplicate the memory-mapped SH-2 features like the cache
interface. Instead, the cache interfaces is described in the device
tree, and new code is added to be able to access the flat device tree
at early boot before it is unflattened.
Support is also added for receiving interrupts on trap numbers in the
range 16 to 31, since the J-Core aic1 interrupt controller generates
these traps. This range was unused but nominally for hardware
exceptions on SH-2, and a few values in this range were used for
exceptions on SH-2A, but SH-2A has its own version of the relevant
code.
No individual cpu subtypes are added for J2 since the intent moving
forward is to represent SoCs with device tree rather than as
hard-coded subtypes in the kernel. The CPU_SUBTYPE_J2 Kconfig item
exists only to fit into the existing cpu selection mechanism until it
is overhauled.
Signed-off-by: Rich Felker <dalias@libc.org>
Diffstat (limited to 'arch/sh/mm/cache.c')
| -rw-r--r-- | arch/sh/mm/cache.c | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/arch/sh/mm/cache.c b/arch/sh/mm/cache.c index 776d664..70cc52f 100644 --- a/arch/sh/mm/cache.c +++ b/arch/sh/mm/cache.c @@ -309,7 +309,11 @@ void __init cpu_cache_init(void) if (unlikely(cache_disabled)) goto skip; - if (boot_cpu_data.family == CPU_FAMILY_SH2) { + if (boot_cpu_data.type == CPU_J2) { + extern void __weak j2_cache_init(void); + + j2_cache_init(); + } else if (boot_cpu_data.family == CPU_FAMILY_SH2) { extern void __weak sh2_cache_init(void); sh2_cache_init(); |