diff options
| author | Paul Mundt <lethal@linux-sh.org> | 2010-10-27 05:36:28 (GMT) |
|---|---|---|
| committer | Paul Mundt <lethal@linux-sh.org> | 2010-10-27 05:36:28 (GMT) |
| commit | 0d338071f2fff7551f9afe22016d9b34b45900b5 (patch) | |
| tree | 74fa0b63383e6695e7b20edec9eb4f61d5eb61b7 /arch/sh | |
| parent | c053784454550cf750399caa65482b31ffbe3c57 (diff) | |
| download | linux-0d338071f2fff7551f9afe22016d9b34b45900b5.tar.xz | |
sh: mach-dreamcast: irq_data conversion.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'arch/sh')
| -rw-r--r-- | arch/sh/boards/mach-dreamcast/irq.c | 17 |
1 files changed, 10 insertions, 7 deletions
diff --git a/arch/sh/boards/mach-dreamcast/irq.c b/arch/sh/boards/mach-dreamcast/irq.c index d932667..72e7ac9 100644 --- a/arch/sh/boards/mach-dreamcast/irq.c +++ b/arch/sh/boards/mach-dreamcast/irq.c @@ -60,8 +60,9 @@ */ /* Disable the hardware event by masking its bit in its EMR */ -static inline void disable_systemasic_irq(unsigned int irq) +static inline void disable_systemasic_irq(struct irq_data *data) { + unsigned int irq = data->irq; __u32 emr = EMR_BASE + (LEVEL(irq) << 4) + (LEVEL(irq) << 2); __u32 mask; @@ -71,8 +72,9 @@ static inline void disable_systemasic_irq(unsigned int irq) } /* Enable the hardware event by setting its bit in its EMR */ -static inline void enable_systemasic_irq(unsigned int irq) +static inline void enable_systemasic_irq(struct irq_data *data) { + unsigned int irq = data->irq; __u32 emr = EMR_BASE + (LEVEL(irq) << 4) + (LEVEL(irq) << 2); __u32 mask; @@ -82,18 +84,19 @@ static inline void enable_systemasic_irq(unsigned int irq) } /* Acknowledge a hardware event by writing its bit back to its ESR */ -static void mask_ack_systemasic_irq(unsigned int irq) +static void mask_ack_systemasic_irq(struct irq_data *data) { + unsigned int irq = data->irq; __u32 esr = ESR_BASE + (LEVEL(irq) << 2); - disable_systemasic_irq(irq); + disable_systemasic_irq(data); outl((1 << EVENT_BIT(irq)), esr); } struct irq_chip systemasic_int = { .name = "System ASIC", - .mask = disable_systemasic_irq, - .mask_ack = mask_ack_systemasic_irq, - .unmask = enable_systemasic_irq, + .irq_mask = disable_systemasic_irq, + .irq_mask_ack = mask_ack_systemasic_irq, + .irq_unmask = enable_systemasic_irq, }; /* |