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authorCyrille Pitchen <cyrille.pitchen@atmel.com>2015-06-09 16:22:14 (GMT)
committerWolfram Sang <wsa@the-dreams.de>2015-06-10 12:51:49 (GMT)
commit93563a6a71bb69dd324fc7354c60fb05f84aae6b (patch)
tree4b8dfdde547bc11cb9e193de1a2026d09e7bbdbb /arch/unicore32
parent0ee04e91eacd15fa95cd60ccccb513c1a5734916 (diff)
downloadlinux-93563a6a71bb69dd324fc7354c60fb05f84aae6b.tar.xz
i2c: at91: fix a race condition when using the DMA controller
For TX transactions, the TXCOMP bit in the Status Register is cleared when the first data is written into the Transmit Holding Register. In the lines from at91_do_twi_transfer(): at91_twi_write_data_dma(dev); at91_twi_write(dev, AT91_TWI_IER, AT91_TWI_TXCOMP); the TXCOMP interrupt may be enabled before the DMA controller has actually started to write into the THR. In such a case, the TXCOMP bit is still set into the Status Register so the interrupt is triggered immediately. The driver understands that a transaction completion has occurred but this transaction hasn't started yet. Hence the TXCOMP interrupt is no longer enabled by at91_do_twi_transfer() but instead by at91_twi_write_data_dma_callback(). Also, the TXCOMP bit in the Status Register in not a clear on read flag but a snapshot of the transmission state at the time the Status Register is read. When a NACK error is dectected by the I2C controller, the TXCOMP, NACK and TXRDY bits are set together to 1 in the SR. If enabled, the TXCOMP interrupt is triggered at the same time. Also setting the TXRDY to 1 triggers the DMA controller to write the next data into the THR. Such a write resets the TXCOMP bit to 0 in the SR. So depending on when the interrupt handler reads the SR, it may fail to detect the NACK error if it relies on the TXCOMP bit. The NACK bit and its interrupt should be used instead. For RX transactions, the TXCOMP bit in the Status Register is cleared when the START bit is set into the Control Register. However to unify the management of the TXCOMP bit when the DMA controller is used, the TXCOMP interrupt is now enabled by the DMA callbacks for both TX and RX transfers. Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com> Cc: stable@vger.kernel.org #3.10 and later Acked-by: Ludovic Desroches <ludovic.desroches@atmel.com> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
Diffstat (limited to 'arch/unicore32')
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