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| author | Andi Kleen <ak@linux.intel.com> | 2015-05-10 19:22:47 (GMT) |
|---|---|---|
| committer | Ingo Molnar <mingo@kernel.org> | 2015-08-04 08:16:58 (GMT) |
| commit | 0f29e573dd32bb8598e74271454e97c962da5e05 (patch) | |
| tree | 25904b376ec79d87574bccbf8a8e0a3cf463ad44 /arch/x86/kernel/cpu/perf_event_intel.c | |
| parent | d8020bee1d0caa90e7b9d6f39ac1fdfaaee7f67f (diff) | |
| download | linux-0f29e573dd32bb8598e74271454e97c962da5e05.tar.xz | |
perf/x86/intel: Move PMU ACK to after LBR read
With Arch Perfmon v4 the PMU ack unfreezes the LBRs. So we need to do
the PMU ack after the LBR reading, otherwise the LBRs would be polluted
by the PMI handler.
This is a minimal change. In principle the ACK could be moved much later.
Signed-off-by: Andi Kleen <ak@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: eranian@google.com
Link: http://lkml.kernel.org/r/1431285767-27027-10-git-send-email-andi@firstfloor.org
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Diffstat (limited to 'arch/x86/kernel/cpu/perf_event_intel.c')
| -rw-r--r-- | arch/x86/kernel/cpu/perf_event_intel.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/x86/kernel/cpu/perf_event_intel.c b/arch/x86/kernel/cpu/perf_event_intel.c index 52c9ded..da93b4b 100644 --- a/arch/x86/kernel/cpu/perf_event_intel.c +++ b/arch/x86/kernel/cpu/perf_event_intel.c @@ -1594,6 +1594,7 @@ static int intel_pmu_handle_irq(struct pt_regs *regs) loops = 0; again: + intel_pmu_lbr_read(); intel_pmu_ack_status(status); if (++loops > 100) { static bool warned = false; @@ -1608,7 +1609,6 @@ again: inc_irq_stat(apic_perf_irqs); - intel_pmu_lbr_read(); /* * Ignore a range of extra bits in status that do not indicate |