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author | Michael S. Tsirkin <mst@redhat.com> | 2014-05-07 13:29:48 (GMT) |
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committer | Paolo Bonzini <pbonzini@redhat.com> | 2014-05-07 16:00:49 (GMT) |
commit | b63cf42fd1d8c18fab71222321aaf356f63089c9 (patch) | |
tree | 6a2f42a81adb0895f6b823c87a8b62700d2f7d82 /arch/x86/kvm/cpuid.c | |
parent | 5f7dde7bbb3c628766676cbd63c0a1834035d6fa (diff) | |
download | linux-b63cf42fd1d8c18fab71222321aaf356f63089c9.tar.xz |
kvm/x86: implement hv EOI assist
It seems that it's easy to implement the EOI assist
on top of the PV EOI feature: simply convert the
page address to the format expected by PV EOI.
Notes:
-"No EOI required" is set only if interrupt injected
is edge triggered; this is true because level interrupts are going
through IOAPIC which disables PV EOI.
In any case, if guest triggers EOI the bit will get cleared on exit.
-For migration, set of HV_X64_MSR_APIC_ASSIST_PAGE sets
KVM_PV_EOI_EN internally, so restoring HV_X64_MSR_APIC_ASSIST_PAGE
seems sufficient
In any case, bit is cleared on exit so worst case it's never re-enabled
-no handling of PV EOI data is performed at HV_X64_MSR_EOI write;
HV_X64_MSR_EOI is a separate optimization - it's an X2APIC
replacement that lets you do EOI with an MSR and not IO.
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Diffstat (limited to 'arch/x86/kvm/cpuid.c')
0 files changed, 0 insertions, 0 deletions