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| author | Cyrill Gorcunov <gorcunov@gmail.com> | 2008-08-11 14:34:08 (GMT) |
|---|---|---|
| committer | Ingo Molnar <mingo@elte.hu> | 2008-08-11 14:43:09 (GMT) |
| commit | 2ae111cdd8d83ebf9de72e36e68a8c84b6ebbeea (patch) | |
| tree | 0ca28a5869a172d0c76caa3ad8271524cc0a733b /arch/x86/mach-default | |
| parent | 15dd859cacf312f606f54502d1f66537a1e5c78c (diff) | |
| download | linux-2ae111cdd8d83ebf9de72e36e68a8c84b6ebbeea.tar.xz | |
x86: apic interrupts - move assignments to irqinit_32.c, v2
64bit mode APIC interrupt handlers are set within irqinit_64.c.
Lets do tha same for 32bit mode which would help in furter code merging.
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
Diffstat (limited to 'arch/x86/mach-default')
| -rw-r--r-- | arch/x86/mach-default/setup.c | 15 |
1 files changed, 0 insertions, 15 deletions
diff --git a/arch/x86/mach-default/setup.c b/arch/x86/mach-default/setup.c index 3d31783..b00f5ad 100644 --- a/arch/x86/mach-default/setup.c +++ b/arch/x86/mach-default/setup.c @@ -36,15 +36,6 @@ void __init pre_intr_init_hook(void) init_ISA_irqs(); } -/* - * IRQ2 is cascade interrupt to second interrupt controller - */ -static struct irqaction irq2 = { - .handler = no_action, - .mask = CPU_MASK_NONE, - .name = "cascade", -}; - /** * intr_init_hook - post gate setup interrupt initialisation * @@ -60,12 +51,6 @@ void __init intr_init_hook(void) if (x86_quirks->arch_intr_init()) return; } -#ifdef CONFIG_X86_LOCAL_APIC - apic_intr_init(); -#endif - - if (!acpi_ioapic) - setup_irq(2, &irq2); } /** |