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authorAndi Kleen <ak@suse.de>2006-01-27 01:03:50 (GMT)
committerGreg Kroah-Hartman <gregkh@suse.de>2006-02-01 02:00:13 (GMT)
commit3103039cc2a8dc6ababc29afac5c3cadbfa69af9 (patch)
treef89e6a1ca25281fbf78f6438c0463d06251ae3a3 /arch/x86_64/pci
parent877be3f0304de16a77f11b2b47f1291b800d5479 (diff)
downloadlinux-3103039cc2a8dc6ababc29afac5c3cadbfa69af9.tar.xz
[PATCH] PCI: handle bogus MCFG entries
Handle more bogus MCFG entries Some Asus P4 boards seem to have broken MCFG tables with only a single entry for busses 0-0. Special case these and assume they mean all busses can be accessed. Signed-off-by: Andi Kleen <ak@suse.de> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
Diffstat (limited to 'arch/x86_64/pci')
-rw-r--r--arch/x86_64/pci/mmconfig.c19
1 files changed, 14 insertions, 5 deletions
diff --git a/arch/x86_64/pci/mmconfig.c b/arch/x86_64/pci/mmconfig.c
index f16c0d5..00d4ddb 100644
--- a/arch/x86_64/pci/mmconfig.c
+++ b/arch/x86_64/pci/mmconfig.c
@@ -29,11 +29,8 @@ static char __iomem *get_virt(unsigned int seg, unsigned bus)
while (1) {
++cfg_num;
- if (cfg_num >= pci_mmcfg_config_num) {
- /* Not found - fall back to type 1. This happens
- e.g. on the internal devices of a K8 northbridge. */
- return NULL;
- }
+ if (cfg_num >= pci_mmcfg_config_num)
+ break;
cfg = pci_mmcfg_virt[cfg_num].cfg;
if (cfg->pci_segment_group_number != seg)
continue;
@@ -41,6 +38,18 @@ static char __iomem *get_virt(unsigned int seg, unsigned bus)
(cfg->end_bus_number >= bus))
return pci_mmcfg_virt[cfg_num].virt;
}
+
+ /* Handle more broken MCFG tables on Asus etc.
+ They only contain a single entry for bus 0-0. Assume
+ this applies to all busses. */
+ cfg = &pci_mmcfg_config[0];
+ if (pci_mmcfg_config_num == 1 &&
+ cfg->pci_segment_group_number == 0 &&
+ (cfg->start_bus_number | cfg->end_bus_number) == 0)
+ return cfg->base_address;
+
+ /* Fall back to type 0 */
+ return 0;
}
static char __iomem *pci_dev_base(unsigned int seg, unsigned int bus, unsigned int devfn)