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| author | Marc Gauthier <marc@tensilica.com> | 2013-01-05 00:57:17 (GMT) |
|---|---|---|
| committer | Chris Zankel <chris@zankel.net> | 2013-02-24 03:12:52 (GMT) |
| commit | 2d1c645cc50b8f5a718b24bad9eb3931e7105d12 (patch) | |
| tree | c385e5064cee10f79b9c359ddd99bd5d1b9f838a /arch/xtensa/include/asm/regs.h | |
| parent | d0b73b488c55df905ea8faaad079f8535629ed26 (diff) | |
| download | linux-2d1c645cc50b8f5a718b24bad9eb3931e7105d12.tar.xz | |
xtensa: dispatch medium-priority interrupts
Add support for dispatching medium-priority interrupts, that is,
interrupts of priority levels 2 to EXCM_LEVEL. IRQ handling may be
preempted by higher priority IRQ.
Signed-off-by: Marc Gauthier <marc@tensilica.com>
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Chris Zankel <chris@zankel.net>
Diffstat (limited to 'arch/xtensa/include/asm/regs.h')
| -rw-r--r-- | arch/xtensa/include/asm/regs.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/xtensa/include/asm/regs.h b/arch/xtensa/include/asm/regs.h index 76096a4..b24de67 100644 --- a/arch/xtensa/include/asm/regs.h +++ b/arch/xtensa/include/asm/regs.h @@ -88,6 +88,7 @@ #define PS_UM_BIT 5 #define PS_EXCM_BIT 4 #define PS_INTLEVEL_SHIFT 0 +#define PS_INTLEVEL_WIDTH 4 #define PS_INTLEVEL_MASK 0x0000000F /* DBREAKCn register fields. */ |