diff options
author | Max Filippov <jcmvbkbc@gmail.com> | 2012-10-14 23:55:38 (GMT) |
---|---|---|
committer | Chris Zankel <chris@zankel.net> | 2012-10-16 04:48:08 (GMT) |
commit | bc5378fcba974317f9657c4fdc78af227e1e1068 (patch) | |
tree | 998b8f8badf1d7a5dc0fd796f3e8501f8c5394ae /arch/xtensa/include | |
parent | f4349b6e01c8927a04795885702a173b6a60573c (diff) | |
download | linux-bc5378fcba974317f9657c4fdc78af227e1e1068.tar.xz |
xtensa: reorganize SR referencing
- reference SRs by names where possible, not by numbers;
- get rid of __stringify around SR names where possible;
- remove unneeded SR names from asm/regs.h;
- add SREG_ prefix to remaining SR names;
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Chris Zankel <chris@zankel.net>
Diffstat (limited to 'arch/xtensa/include')
-rw-r--r-- | arch/xtensa/include/asm/atomic.h | 12 | ||||
-rw-r--r-- | arch/xtensa/include/asm/cacheflush.h | 2 | ||||
-rw-r--r-- | arch/xtensa/include/asm/cmpxchg.h | 4 | ||||
-rw-r--r-- | arch/xtensa/include/asm/coprocessor.h | 5 | ||||
-rw-r--r-- | arch/xtensa/include/asm/delay.h | 2 | ||||
-rw-r--r-- | arch/xtensa/include/asm/irqflags.h | 4 | ||||
-rw-r--r-- | arch/xtensa/include/asm/mmu_context.h | 4 | ||||
-rw-r--r-- | arch/xtensa/include/asm/regs.h | 55 | ||||
-rw-r--r-- | arch/xtensa/include/asm/timex.h | 8 | ||||
-rw-r--r-- | arch/xtensa/include/asm/tlbflush.h | 8 |
10 files changed, 33 insertions, 71 deletions
diff --git a/arch/xtensa/include/asm/atomic.h b/arch/xtensa/include/asm/atomic.h index b409893..24f50ca 100644 --- a/arch/xtensa/include/asm/atomic.h +++ b/arch/xtensa/include/asm/atomic.h @@ -73,7 +73,7 @@ static inline void atomic_add(int i, atomic_t * v) "l32i %0, %2, 0 \n\t" "add %0, %0, %1 \n\t" "s32i %0, %2, 0 \n\t" - "wsr a15, "__stringify(PS)" \n\t" + "wsr a15, ps \n\t" "rsync \n" : "=&a" (vval) : "a" (i), "a" (v) @@ -97,7 +97,7 @@ static inline void atomic_sub(int i, atomic_t *v) "l32i %0, %2, 0 \n\t" "sub %0, %0, %1 \n\t" "s32i %0, %2, 0 \n\t" - "wsr a15, "__stringify(PS)" \n\t" + "wsr a15, ps \n\t" "rsync \n" : "=&a" (vval) : "a" (i), "a" (v) @@ -118,7 +118,7 @@ static inline int atomic_add_return(int i, atomic_t * v) "l32i %0, %2, 0 \n\t" "add %0, %0, %1 \n\t" "s32i %0, %2, 0 \n\t" - "wsr a15, "__stringify(PS)" \n\t" + "wsr a15, ps \n\t" "rsync \n" : "=&a" (vval) : "a" (i), "a" (v) @@ -137,7 +137,7 @@ static inline int atomic_sub_return(int i, atomic_t * v) "l32i %0, %2, 0 \n\t" "sub %0, %0, %1 \n\t" "s32i %0, %2, 0 \n\t" - "wsr a15, "__stringify(PS)" \n\t" + "wsr a15, ps \n\t" "rsync \n" : "=&a" (vval) : "a" (i), "a" (v) @@ -260,7 +260,7 @@ static inline void atomic_clear_mask(unsigned int mask, atomic_t *v) "xor %1, %4, %3 \n\t" "and %0, %0, %4 \n\t" "s32i %0, %2, 0 \n\t" - "wsr a15, "__stringify(PS)" \n\t" + "wsr a15, ps \n\t" "rsync \n" : "=&a" (vval), "=a" (mask) : "a" (v), "a" (all_f), "1" (mask) @@ -277,7 +277,7 @@ static inline void atomic_set_mask(unsigned int mask, atomic_t *v) "l32i %0, %2, 0 \n\t" "or %0, %0, %1 \n\t" "s32i %0, %2, 0 \n\t" - "wsr a15, "__stringify(PS)" \n\t" + "wsr a15, ps \n\t" "rsync \n" : "=&a" (vval) : "a" (mask), "a" (v) diff --git a/arch/xtensa/include/asm/cacheflush.h b/arch/xtensa/include/asm/cacheflush.h index 376cd9d..569fec4 100644 --- a/arch/xtensa/include/asm/cacheflush.h +++ b/arch/xtensa/include/asm/cacheflush.h @@ -165,7 +165,7 @@ extern void copy_from_user_page(struct vm_area_struct*, struct page*, static inline u32 xtensa_get_cacheattr(void) { u32 r; - asm volatile(" rsr %0, CACHEATTR" : "=a"(r)); + asm volatile(" rsr %0, cacheattr" : "=a"(r)); return r; } diff --git a/arch/xtensa/include/asm/cmpxchg.h b/arch/xtensa/include/asm/cmpxchg.h index e321490..64dad04 100644 --- a/arch/xtensa/include/asm/cmpxchg.h +++ b/arch/xtensa/include/asm/cmpxchg.h @@ -27,7 +27,7 @@ __cmpxchg_u32(volatile int *p, int old, int new) "bne %0, %2, 1f \n\t" "s32i %3, %1, 0 \n\t" "1: \n\t" - "wsr a15, "__stringify(PS)" \n\t" + "wsr a15, ps \n\t" "rsync \n\t" : "=&a" (old) : "a" (p), "a" (old), "r" (new) @@ -97,7 +97,7 @@ static inline unsigned long xchg_u32(volatile int * m, unsigned long val) __asm__ __volatile__("rsil a15, "__stringify(LOCKLEVEL)"\n\t" "l32i %0, %1, 0 \n\t" "s32i %2, %1, 0 \n\t" - "wsr a15, "__stringify(PS)" \n\t" + "wsr a15, ps \n\t" "rsync \n\t" : "=&a" (tmp) : "a" (m), "a" (val) diff --git a/arch/xtensa/include/asm/coprocessor.h b/arch/xtensa/include/asm/coprocessor.h index 75c94a1..677501b 100644 --- a/arch/xtensa/include/asm/coprocessor.h +++ b/arch/xtensa/include/asm/coprocessor.h @@ -94,11 +94,10 @@ #if XCHAL_HAVE_CP #define RSR_CPENABLE(x) do { \ - __asm__ __volatile__("rsr %0," __stringify(CPENABLE) : "=a" (x)); \ + __asm__ __volatile__("rsr %0, cpenable" : "=a" (x)); \ } while(0); #define WSR_CPENABLE(x) do { \ - __asm__ __volatile__("wsr %0," __stringify(CPENABLE) "; rsync" \ - :: "a" (x)); \ + __asm__ __volatile__("wsr %0, cpenable; rsync" :: "a" (x)); \ } while(0); #endif /* XCHAL_HAVE_CP */ diff --git a/arch/xtensa/include/asm/delay.h b/arch/xtensa/include/asm/delay.h index e1d8c9e..58c0a4f 100644 --- a/arch/xtensa/include/asm/delay.h +++ b/arch/xtensa/include/asm/delay.h @@ -27,7 +27,7 @@ static inline void __delay(unsigned long loops) static __inline__ u32 xtensa_get_ccount(void) { u32 ccount; - asm volatile ("rsr %0, 234; # CCOUNT\n" : "=r" (ccount)); + asm volatile ("rsr %0, ccount\n" : "=r" (ccount)); return ccount; } diff --git a/arch/xtensa/include/asm/irqflags.h b/arch/xtensa/include/asm/irqflags.h index dae9a8b..f865b1c 100644 --- a/arch/xtensa/include/asm/irqflags.h +++ b/arch/xtensa/include/asm/irqflags.h @@ -16,7 +16,7 @@ static inline unsigned long arch_local_save_flags(void) { unsigned long flags; - asm volatile("rsr %0,"__stringify(PS) : "=a" (flags)); + asm volatile("rsr %0, ps" : "=a" (flags)); return flags; } @@ -41,7 +41,7 @@ static inline void arch_local_irq_enable(void) static inline void arch_local_irq_restore(unsigned long flags) { - asm volatile("wsr %0, "__stringify(PS)" ; rsync" + asm volatile("wsr %0, ps; rsync" :: "a" (flags) : "memory"); } diff --git a/arch/xtensa/include/asm/mmu_context.h b/arch/xtensa/include/asm/mmu_context.h index dbd8731..feb10af 100644 --- a/arch/xtensa/include/asm/mmu_context.h +++ b/arch/xtensa/include/asm/mmu_context.h @@ -51,14 +51,14 @@ extern unsigned long asid_cache; static inline void set_rasid_register (unsigned long val) { - __asm__ __volatile__ (" wsr %0, "__stringify(RASID)"\n\t" + __asm__ __volatile__ (" wsr %0, rasid\n\t" " isync\n" : : "a" (val)); } static inline unsigned long get_rasid_register (void) { unsigned long tmp; - __asm__ __volatile__ (" rsr %0,"__stringify(RASID)"\n\t" : "=a" (tmp)); + __asm__ __volatile__ (" rsr %0, rasid\n\t" : "=a" (tmp)); return tmp; } diff --git a/arch/xtensa/include/asm/regs.h b/arch/xtensa/include/asm/regs.h index a3075b1..8a8aa61 100644 --- a/arch/xtensa/include/asm/regs.h +++ b/arch/xtensa/include/asm/regs.h @@ -27,52 +27,15 @@ /* Special registers. */ -#define LBEG 0 -#define LEND 1 -#define LCOUNT 2 -#define SAR 3 -#define BR 4 -#define SCOMPARE1 12 -#define ACCHI 16 -#define ACCLO 17 -#define MR 32 -#define WINDOWBASE 72 -#define WINDOWSTART 73 -#define PTEVADDR 83 -#define RASID 90 -#define ITLBCFG 91 -#define DTLBCFG 92 -#define IBREAKENABLE 96 -#define DDR 104 -#define IBREAKA 128 -#define DBREAKA 144 -#define DBREAKC 160 -#define EPC 176 -#define EPC_1 177 -#define DEPC 192 -#define EPS 192 -#define EPS_1 193 -#define EXCSAVE 208 -#define EXCSAVE_1 209 -#define INTERRUPT 226 -#define INTENABLE 228 -#define PS 230 -#define THREADPTR 231 -#define EXCCAUSE 232 -#define DEBUGCAUSE 233 -#define CCOUNT 234 -#define PRID 235 -#define ICOUNT 236 -#define ICOUNTLEVEL 237 -#define EXCVADDR 238 -#define CCOMPARE 240 -#define MISC_SR 244 - -/* Special names for read-only and write-only interrupt registers. */ - -#define INTREAD 226 -#define INTSET 226 -#define INTCLEAR 227 +#define SREG_MR 32 +#define SREG_IBREAKA 128 +#define SREG_DBREAKA 144 +#define SREG_DBREAKC 160 +#define SREG_EPC 176 +#define SREG_EPS 192 +#define SREG_EXCSAVE 208 +#define SREG_CCOMPARE 240 +#define SREG_MISC 244 /* EXCCAUSE register fields */ diff --git a/arch/xtensa/include/asm/timex.h b/arch/xtensa/include/asm/timex.h index 053bc42..175b3d5 100644 --- a/arch/xtensa/include/asm/timex.h +++ b/arch/xtensa/include/asm/timex.h @@ -63,10 +63,10 @@ extern cycles_t cacheflush_time; * Register access. */ -#define WSR_CCOUNT(r) asm volatile ("wsr %0,"__stringify(CCOUNT) :: "a" (r)) -#define RSR_CCOUNT(r) asm volatile ("rsr %0,"__stringify(CCOUNT) : "=a" (r)) -#define WSR_CCOMPARE(x,r) asm volatile ("wsr %0,"__stringify(CCOMPARE)"+"__stringify(x) :: "a"(r)) -#define RSR_CCOMPARE(x,r) asm volatile ("rsr %0,"__stringify(CCOMPARE)"+"__stringify(x) : "=a"(r)) +#define WSR_CCOUNT(r) asm volatile ("wsr %0, ccount" :: "a" (r)) +#define RSR_CCOUNT(r) asm volatile ("rsr %0, ccount" : "=a" (r)) +#define WSR_CCOMPARE(x,r) asm volatile ("wsr %0,"__stringify(SREG_CCOMPARE)"+"__stringify(x) :: "a"(r)) +#define RSR_CCOMPARE(x,r) asm volatile ("rsr %0,"__stringify(SREG_CCOMPARE)"+"__stringify(x) : "=a"(r)) static inline unsigned long get_ccount (void) { diff --git a/arch/xtensa/include/asm/tlbflush.h b/arch/xtensa/include/asm/tlbflush.h index 46d2400..43dd348 100644 --- a/arch/xtensa/include/asm/tlbflush.h +++ b/arch/xtensa/include/asm/tlbflush.h @@ -86,26 +86,26 @@ static inline void invalidate_dtlb_entry_no_isync (unsigned entry) static inline void set_itlbcfg_register (unsigned long val) { - __asm__ __volatile__("wsr %0, "__stringify(ITLBCFG)"\n\t" "isync\n\t" + __asm__ __volatile__("wsr %0, itlbcfg\n\t" "isync\n\t" : : "a" (val)); } static inline void set_dtlbcfg_register (unsigned long val) { - __asm__ __volatile__("wsr %0, "__stringify(DTLBCFG)"; dsync\n\t" + __asm__ __volatile__("wsr %0, dtlbcfg; dsync\n\t" : : "a" (val)); } static inline void set_ptevaddr_register (unsigned long val) { - __asm__ __volatile__(" wsr %0, "__stringify(PTEVADDR)"; isync\n" + __asm__ __volatile__(" wsr %0, ptevaddr; isync\n" : : "a" (val)); } static inline unsigned long read_ptevaddr_register (void) { unsigned long tmp; - __asm__ __volatile__("rsr %0, "__stringify(PTEVADDR)"\n\t" : "=a" (tmp)); + __asm__ __volatile__("rsr %0, ptevaddr\n\t" : "=a" (tmp)); return tmp; } |