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authorJiada Wang <jiada_wang@mentor.com>2014-05-15 01:22:13 (GMT)
committerVinod Koul <vinod.koul@intel.com>2014-06-01 16:52:26 (GMT)
commitffe59b29308791c9600ab86de2ca070d742c107d (patch)
treeb4060dc64613790759022ad918cba2e91f5a5a3b /arch/xtensa/kernel
parenta15783c34f6304e85f7d810e71316c1c3ba1fe69 (diff)
downloadlinux-ffe59b29308791c9600ab86de2ca070d742c107d.tar.xz
dmaengine: imx: correct sdmac->status for cyclic dma tx
In cyclic dma tx's handler sdma_handle_channel_loop(), SDMA channel statue is set to either DMA_ERROR or DMA_IN_PROGRESS based on each period's status. This has the following issues: 1) If one period's status is BD_RROR, then channel status will be set to DMA_ERROR, but it will be overwritten to DMA_IN_PROGRESS if the following periods are OK. 2) DMA client may call sdma_control(DMA_TERMINATE_ALL) to stop the cyclic dma operation, sdma channel status will be set to DMA_ERROR, but if after this handler is called, then again the channel status will be overwritten to DMA_IN_PROGRESS. Then the following dmaengine_prep_dma_cyclic() will always fail, as channel status is DMA_IN_PROGRESS. As in cyclic dma tx, channel status will be initially set to DMA_IN_PROGRESS, driver only needs to change it to DMA_ERROR, when something wrong happens (one period status is wrong, or stoped by client explicitly). Signed-off-by: Jiada Wang <jiada_wang@mentor.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
Diffstat (limited to 'arch/xtensa/kernel')
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