diff options
| author | Zhang Ying-22455 <ying.zhang22455@nxp.com> | 2017-06-16 04:52:11 (GMT) |
|---|---|---|
| committer | Xie Xiaobo <xiaobo.xie@nxp.com> | 2017-07-14 09:57:28 (GMT) |
| commit | 8501f51e4aa8efb6aa81d4ab8eedb313e3c966f8 (patch) | |
| tree | ce3a22681165193da5cbe3003d681bd98f3451fa /arch | |
| parent | 7b0ec1f64f2deaa6cb7aca4e55dfd9dbce2688c8 (diff) | |
| download | linux-8501f51e4aa8efb6aa81d4ab8eedb313e3c966f8.tar.xz | |
arm64: dts: ls1088ardb: correct the base address of watchdog
The base address of watchdog unit is incorrect lead to the
watchdog timer is not registered.
Signed-off-by: Zhang Ying-22455 <ying.zhang22455@nxp.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi | 24 |
1 files changed, 12 insertions, 12 deletions
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi index d437783..d832604 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi @@ -352,44 +352,44 @@ clock-names = "apb_pclk", "wdog_clk"; }; - cluster2_core0_watchdog: wdt@c100000 { + cluster1_core2_watchdog: wdt@c020000 { compatible = "arm,sp805-wdt", "arm,primecell"; - reg = <0x0 0xc100000 0x0 0x1000>; + reg = <0x0 0xc020000 0x0 0x1000>; clocks = <&clockgen 4 3>, <&clockgen 4 3>; clock-names = "apb_pclk", "wdog_clk"; }; - cluster2_core1_watchdog: wdt@c110000 { + cluster1_core3_watchdog: wdt@c030000 { compatible = "arm,sp805-wdt", "arm,primecell"; - reg = <0x0 0xc110000 0x0 0x1000>; + reg = <0x0 0xc030000 0x0 0x1000>; clocks = <&clockgen 4 3>, <&clockgen 4 3>; clock-names = "apb_pclk", "wdog_clk"; }; - cluster3_core0_watchdog: wdt@c200000 { + cluster2_core0_watchdog: wdt@c100000 { compatible = "arm,sp805-wdt", "arm,primecell"; - reg = <0x0 0xc200000 0x0 0x1000>; + reg = <0x0 0xc100000 0x0 0x1000>; clocks = <&clockgen 4 3>, <&clockgen 4 3>; clock-names = "apb_pclk", "wdog_clk"; }; - cluster3_core1_watchdog: wdt@c210000 { + cluster2_core1_watchdog: wdt@c110000 { compatible = "arm,sp805-wdt", "arm,primecell"; - reg = <0x0 0xc210000 0x0 0x1000>; + reg = <0x0 0xc110000 0x0 0x1000>; clocks = <&clockgen 4 3>, <&clockgen 4 3>; clock-names = "apb_pclk", "wdog_clk"; }; - cluster4_core0_watchdog: wdt@c300000 { + cluster2_core2_watchdog: wdt@c120000 { compatible = "arm,sp805-wdt", "arm,primecell"; - reg = <0x0 0xc300000 0x0 0x1000>; + reg = <0x0 0xc120000 0x0 0x1000>; clocks = <&clockgen 4 3>, <&clockgen 4 3>; clock-names = "apb_pclk", "wdog_clk"; }; - cluster4_core1_watchdog: wdt@c310000 { + cluster2_core3_watchdog: wdt@c130000 { compatible = "arm,sp805-wdt", "arm,primecell"; - reg = <0x0 0xc310000 0x0 0x1000>; + reg = <0x0 0xc130000 0x0 0x1000>; clocks = <&clockgen 4 3>, <&clockgen 4 3>; clock-names = "apb_pclk", "wdog_clk"; }; |