diff options
| author | Steven J. Hill <Steven.Hill@imgtec.com> | 2013-10-09 15:47:23 (GMT) |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2014-01-22 19:18:57 (GMT) |
| commit | 5cf8b2409c8c08f7505925d2ba78f71b362d902e (patch) | |
| tree | 600cc2e0e05cbc9fd9756d33bfdfece835fd8dbf /arch | |
| parent | c2c2a644935dcdb287a87bf4f3cccd13bd8d3468 (diff) | |
| download | linux-5cf8b2409c8c08f7505925d2ba78f71b362d902e.tar.xz | |
MIPS: GIC: Send IPIs using the GIC
If GIC is present, then use it to send IPIs between the cores.
Using GIC for IPIs is simpler and is usable for multicore
systems compared to the existing way of doing IPIs where all VPEs
had to be disabled for another VPE to access the Cause register
in one of the TCs and enable all the VPEs back.
Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com>
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Signed-off-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/6040/
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/mips/kernel/smp-mt.c | 27 |
1 files changed, 27 insertions, 0 deletions
diff --git a/arch/mips/kernel/smp-mt.c b/arch/mips/kernel/smp-mt.c index 35f8d22..0fb8cef 100644 --- a/arch/mips/kernel/smp-mt.c +++ b/arch/mips/kernel/smp-mt.c @@ -113,12 +113,39 @@ static void __init smvp_tc_init(unsigned int tc, unsigned int mvpconf0) write_tc_c0_tchalt(TCHALT_H); } +#ifdef CONFIG_IRQ_GIC +static void mp_send_ipi_single(int cpu, unsigned int action) +{ + unsigned long flags; + + local_irq_save(flags); + + switch (action) { + case SMP_CALL_FUNCTION: + gic_send_ipi(plat_ipi_call_int_xlate(cpu)); + break; + + case SMP_RESCHEDULE_YOURSELF: + gic_send_ipi(plat_ipi_resched_int_xlate(cpu)); + break; + } + + local_irq_restore(flags); +} +#endif + static void vsmp_send_ipi_single(int cpu, unsigned int action) { int i; unsigned long flags; int vpflags; +#ifdef CONFIG_IRQ_GIC + if (gic_present) { + mp_send_ipi_single(cpu, action); + return; + } +#endif local_irq_save(flags); vpflags = dvpe(); /* can't access the other CPU's registers whilst MVPE enabled */ |