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| author | Joseph Lo <josephl@nvidia.com> | 2013-10-11 09:57:31 (GMT) |
|---|---|---|
| committer | Stephen Warren <swarren@nvidia.com> | 2013-10-18 22:28:08 (GMT) |
| commit | d127e9c5c5bc1ee22a7b1fe804397cddd132f756 (patch) | |
| tree | 2500a25b3a79dd3b593f8ad043bfcfacb0e63fa0 /arch | |
| parent | 9997e62682e0fe68566c88f70ed320ded4e16529 (diff) | |
| download | linux-d127e9c5c5bc1ee22a7b1fe804397cddd132f756.tar.xz | |
ARM: tegra: make tegra_resume can work with current and later chips
Because the CPU0 was the first up and the last down core when cluster
power up/down or platform suspend. So only CPU0 needs the rest of the
functions to reset flow controller and re-enable SCU and L2. We also
move the L2 init function for Cortex-A15 to there. The secondery CPU
can just call cpu_resume.
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/mach-tegra/reset-handler.S | 13 |
1 files changed, 5 insertions, 8 deletions
diff --git a/arch/arm/mach-tegra/reset-handler.S b/arch/arm/mach-tegra/reset-handler.S index f527b2c..8c1ba4f 100644 --- a/arch/arm/mach-tegra/reset-handler.S +++ b/arch/arm/mach-tegra/reset-handler.S @@ -45,17 +45,11 @@ ENTRY(tegra_resume) check_cpu_part_num 0xc09, r8, r9 bleq v7_invalidate_l1 - blne tegra_init_l2_for_a15 cpu_id r0 - tegra_get_soc_id TEGRA_APB_MISC_BASE, r6 - cmp r6, #TEGRA114 - beq no_cpu0_chk - cmp r0, #0 @ CPU0? THUMB( it ne ) bne cpu_resume @ no -no_cpu0_chk: /* Are we on Tegra20? */ cmp r6, #TEGRA20 @@ -75,7 +69,7 @@ no_cpu0_chk: mov32 r9, 0xc09 cmp r8, r9 - bne not_ca9 + bne end_ca9_scu_l2_resume #ifdef CONFIG_HAVE_ARM_SCU /* enable SCU */ mov32 r0, TEGRA_ARM_PERIF_BASE @@ -86,7 +80,10 @@ no_cpu0_chk: /* L2 cache resume & re-enable */ l2_cache_resume r0, r1, r2, l2x0_saved_regs_addr -not_ca9: +end_ca9_scu_l2_resume: + mov32 r9, 0xc0f + cmp r8, r9 + bleq tegra_init_l2_for_a15 b cpu_resume ENDPROC(tegra_resume) |